[PATCH 02/13] drm/i915: Apply the 16Gb DIMM w/a only for the platforms that need it

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

Currently the code assumes that every platform except dg2 need the
16Gb DIMM w/a, while in reality it's only needed by skl and icl (and
derivatives). Switch to a more specific platform check.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index b7482d428868..8c434bc96971 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3174,11 +3174,19 @@ void skl_watermark_ipc_init(struct intel_display 
*display)
        skl_watermark_ipc_update(display);
 }
 
+static bool need_16gb_dimm_wa(struct intel_display *display)
+{
+       const struct dram_info *dram_info = intel_dram_info(display->drm);
+
+       return (display->platform.skylake || display->platform.kabylake ||
+               display->platform.coffeelake || display->platform.cometlake ||
+               DISPLAY_VER(display) == 11) && dram_info->has_16gb_dimms;
+}
+
 static void
 adjust_wm_latency(struct intel_display *display,
                  u16 wm[], int num_levels, int read_latency)
 {
-       const struct dram_info *dram_info = intel_dram_info(display->drm);
        int i, level;
 
        /*
@@ -3214,7 +3222,7 @@ adjust_wm_latency(struct intel_display *display,
         * any underrun. If not able to get DIMM info assume 16Gb+ DIMM
         * to avoid any underrun.
         */
-       if (!display->platform.dg2 && dram_info->has_16gb_dimms)
+       if (need_16gb_dimm_wa(display))
                wm[0] += 1;
 }
 
-- 
2.49.1