On Tue, Sep 16, 2025 at 01:29:17PM +0300, Luca Coelho wrote:
> On Fri, 2025-09-05 at 17:58 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > Some systems (eg. LNL Lenovo Thinkapd X1 Carbon) declare
> > semi-bogus non-monotonic WM latency values:
> > WM0 latency not provided
> > WM1 latency 100 usec
> > WM2 latency 100 usec
> > WM3 latency 100 usec
> > WM4 latency 93 usec
> > WM5 latency 100 usec
> >
> > Apparently Windows just papers over the issue by bumping the
> > latencies for the higher watermark levels to make them monotonic
> > again. Do the same.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index e11ba1a822f4..d334cc661328 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -3238,6 +3238,19 @@ static void sanitize_wm_latency(struct intel_display
> > *display)
> > }
> > }
> >
> > +static void make_wm_latency_monotonic(struct intel_display *display)
> > +{
> > + u16 *wm = display->wm.skl_latency;
> > + int level, num_levels = display->wm.num_levels;
> > +
> > + for (level = 1; level < num_levels; level++) {
> > + if (wm[level] == 0)
> > + break;
> > +
> > + wm[level] = max(wm[level], wm[level-1]);
> > + }
> > +}
> > +
>
> What if, for instance, we have:
>
> WM0 latency not provided
> WM1 latency 200 usec
> WM2 latency 100 usec
> WM3 latency 100 usec
> WM4 latency 100 usec
> WM5 latency 100 usec
>
> Do we really want to set them all to be 200 usec? Maybe multiples of
> the minimum we have would still be fine?
The latencies are supposed to increase as you go along,
each subsequent level corresponding to some deeper pkgC state.
>
> What's the actual reason for this "papering over"? Is it to synchronize
> timers?
Dunno why Windows started to do this (as opposed to complaining and
telling people to fix their pcode firmware to correctly populate the
latencies). But since it does that it seems likely we might run into
more cases like this in the future.
--
Ville Syrjälä
Intel
