On Fri, 2025-09-05 at 17:58 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> While the spec only asks us to do the WM0 latency bump for 16Gb
> DRAM devices I believe we should apply it for larger DRAM chips.
> At the time the w/a was added there were no larger chips on
> the market, but I think I've seen at least 32Gb DDR4 chips
> being available these days.
>
> Whether it's possible to actually find suitable DIMMs for the
> affected systems with largers chips I don't know. Also it's
> not known whether the 1 usec latency bump would be sufficient
> for larger chips. Someone would need to find such DIMMs and
> test this. Fortunately we do have a bit of extra latency already
> with the 1 usec bump, as the actual requirement was .4 usec for
> for 16Gb chips.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
Sound reasonable.
Reviewed-by: Luca Coelho <luciano.coe...@intel.com>
--
Cheers,
Luca.
> drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
> drivers/gpu/drm/i915/soc/intel_dram.c | 10 +++++-----
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 0b9c86042e78..b7482d428868 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3209,9 +3209,9 @@ adjust_wm_latency(struct intel_display *display,
> }
>
> /*
> - * WA Level-0 adjustment for 16Gb DIMMs: SKL+
> + * WA Level-0 adjustment for 16Gb+ DIMMs: SKL+
> * If we could not get dimm info enable this WA to prevent from
> - * any underrun. If not able to get DIMM info assume 16Gb DIMM
> + * any underrun. If not able to get DIMM info assume 16Gb+ DIMM
> * to avoid any underrun.
> */
> if (!display->platform.dg2 && dram_info->has_16gb_dimms)
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
> b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 149527827624..8e81573022ff 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -335,7 +335,7 @@ static bool
> skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
> {
> /* Convert total Gb to Gb per DRAM device */
> - return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
> + return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) >= 16;
> }
>
> static void
> @@ -354,7 +354,7 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
> }
>
> drm_dbg_kms(&i915->drm,
> - "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb
> DIMMs: %s\n",
> + "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb+
> DIMMs: %s\n",
> channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
> str_yes_no(skl_is_16gb_dimm(dimm)));
> }
> @@ -384,7 +384,7 @@ skl_dram_get_channel_info(struct drm_i915_private *i915,
> ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
> skl_is_16gb_dimm(&ch->dimm_s);
>
> - drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
> + drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n",
> channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
>
> return 0;
> @@ -406,7 +406,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915,
> struct dram_info *dram
> u32 val;
> int ret;
>
> - /* Assume 16Gb DIMMs are present until proven otherwise */
> + /* Assume 16Gb+ DIMMs are present until proven otherwise */
> dram_info->has_16gb_dimms = true;
>
> val = intel_uncore_read(&i915->uncore,
> @@ -438,7 +438,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915,
> struct dram_info *dram
> drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
> str_yes_no(dram_info->symmetric_memory));
>
> - drm_dbg_kms(&i915->drm, "16Gb DIMMs: %s\n",
> + drm_dbg_kms(&i915->drm, "16Gb+ DIMMs: %s\n",
> str_yes_no(dram_info->has_16gb_dimms));
>
> return 0;
