> -----Original Message-----
> From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Tuesday, 5 August 2025 10.37
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using
> the pin assignment enum
>
> Pass around the pin assignment value via the corresponding enum instead of a
> plain integer.
>
> While at it rename intel_tc_port_get_pin_assignment_mask() to
> intel_tc_port_get_pin_assignment(), since the value returned is
> not a mask.
>
Reviewed-by: Mika Kahola <mika.kah...@intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_tc.c | 14 ++++++++------
> drivers/gpu/drm/i915/display/intel_tc.h | 3 ++-
> 3 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 866ed3e466645..2ed9fdd499c39 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2166,7 +2166,8 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port, {
> struct intel_display *display = to_intel_display(crtc_state);
> enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
> - u32 ln0, ln1, pin_assignment;
> + enum intel_tc_pin_assignment pin_assignment;
> + u32 ln0, ln1;
> u8 width;
>
> if (DISPLAY_VER(display) >= 14)
> @@ -2188,11 +2189,11 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port,
> ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>
> /* DPPATC */
> - pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
> + pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
> width = crtc_state->lane_count;
>
> switch (pin_assignment) {
> - case 0x0:
> + case INTEL_TC_PIN_ASSIGNMENT_NONE:
> drm_WARN_ON(display->drm,
> !intel_tc_port_in_legacy_mode(dig_port));
> if (width == 1) {
> @@ -2202,20 +2203,20 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port,
> ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> }
> break;
> - case 0x1:
> + case INTEL_TC_PIN_ASSIGNMENT_A:
> if (width == 4) {
> ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> }
> break;
> - case 0x2:
> + case INTEL_TC_PIN_ASSIGNMENT_B:
> if (width == 2) {
> ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
> ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> }
> break;
> - case 0x3:
> - case 0x5:
> + case INTEL_TC_PIN_ASSIGNMENT_C:
> + case INTEL_TC_PIN_ASSIGNMENT_E:
> if (width == 1) {
> ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> @@ -2224,8 +2225,8 @@ icl_program_mg_dp_mode(struct intel_digital_port
> *dig_port,
> ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
> }
> break;
> - case 0x4:
> - case 0x6:
> + case INTEL_TC_PIN_ASSIGNMENT_D:
> + case INTEL_TC_PIN_ASSIGNMENT_F:
> if (width == 1) {
> ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 9a40ad07830f5..05df252640f46 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -277,7 +277,8 @@ static u32 intel_tc_port_get_lane_mask(struct
> intel_digital_port *dig_port)
> return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> }
>
> -u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port)
> +enum intel_tc_pin_assignment
> +intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port)
> {
> struct intel_display *display = to_intel_display(dig_port);
> struct intel_tc_port *tc = to_tc_port(dig_port); @@ -299,8 +300,9 @@
> static int lnl_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
> struct intel_display *display = to_intel_display(dig_port);
> enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
> struct intel_tc_port *tc = to_tc_port(dig_port);
> + enum intel_tc_pin_assignment pin_assignment;
> intel_wakeref_t wakeref;
> - u32 val, pin_assignment;
> + u32 val;
>
> with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); @@
> -327,13 +329,13 @@ static int
> lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
>
> static int mtl_tc_port_get_max_lane_count(struct intel_digital_port
> *dig_port) {
> - u32 pin_mask;
> + enum intel_tc_pin_assignment pin_assignment;
>
> - pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
> + pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
>
> - switch (pin_mask) {
> + switch (pin_assignment) {
> default:
> - MISSING_CASE(pin_mask);
> + MISSING_CASE(pin_assignment);
> fallthrough;
> case INTEL_TC_PIN_ASSIGNMENT_D:
> return 2;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> b/drivers/gpu/drm/i915/display/intel_tc.h
> index d35d9aae3b889..3ecb3de54e874 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -88,7 +88,8 @@ bool intel_tc_port_handles_hpd_glitches(struct
> intel_digital_port *dig_port);
>
> bool intel_tc_port_connected(struct intel_encoder *encoder);
>
> -u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port);
> +enum intel_tc_pin_assignment
> +intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port);
> int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port); void
> intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
> int required_lanes);
> --
> 2.49.1
