On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com> wrote:
> Add DC Balance params to crtc_state, also add state checker
> params for related properties.
>
> --v3:
> - Seggregate crtc_state params with this patch. (Ankit)
>
> --v4:
> - Update commit message and header. (Ankit)
> - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++
> .../drm/i915/display/intel_display_types.h | 7 ++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++++++++++
> 3 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index de8bf292897c..939366ecea85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5429,6 +5429,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> PIPE_CONF_CHECK_BOOL(cmrr.enable);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
> + PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
> }
>
> if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 30c7315fc25e..e5461900c15b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1316,6 +1316,13 @@ struct intel_crtc_state {
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> u32 vsync_end, vsync_start;
> + struct {
> + bool enable;
> + u16 vmin, vmax;
> + u16 guardband, slope;
> + u16 max_increase, max_decrease;
> + u16 vblank_target;
> + } dc_balance;
> } vrr;
>
> /* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d7bc35b07bab..4016da70ece2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_dmc_regs.h"
Please keep the includes sorted.
> #include "intel_vrr.h"
> #include "intel_vrr_regs.h"
>
> @@ -699,6 +700,8 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum pipe pipe = crtc->pipe;
> u32 trans_vrr_ctl, trans_vrr_vsync;
> bool vrr_enable;
>
> @@ -761,6 +764,25 @@ void intel_vrr_get_config(struct intel_crtc_state
> *crtc_state)
> else
> crtc_state->vrr.enable = vrr_enable;
>
> + if (HAS_VRR_DC_BALANCE(display)) {
> + crtc_state->vrr.dc_balance.vmin =
> + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ?
> + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0;
> + crtc_state->vrr.dc_balance.vmax =
> + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ?
> + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0;
> + crtc_state->vrr.dc_balance.guardband =
> + intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
> + crtc_state->vrr.dc_balance.max_increase =
> + intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
> + crtc_state->vrr.dc_balance.max_decrease =
> + intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
> + crtc_state->vrr.dc_balance.slope =
> + intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
> + crtc_state->vrr.dc_balance.vblank_target =
> + intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
> + }
> +
> /*
> * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for
> mode_flags.
> * Since CMRR is currently disabled, set this flag for VRR for now.
--
Jani Nikula, Intel
