From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Restructure bits for VRR enablement.
--v2:
- Separate multiple enablement from one patch.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 29 ++++++++++++------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index ce23bcab1033..91d4fa0d2bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -624,6 +624,7 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 ctl;
if (!crtc_state->vrr.enable)
return;
@@ -638,19 +639,6 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
- if (!intel_vrr_always_use_vrr_tg(display)) {
- intel_vrr_set_db_point_and_transmission_line(crtc_state);
-
- if (crtc_state->cmrr.enable) {
- intel_de_write(display, TRANS_VRR_CTL(display,
cpu_transcoder),
- VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE
|
- trans_vrr_ctl(crtc_state));
- } else {
- intel_de_write(display, TRANS_VRR_CTL(display,
cpu_transcoder),
- VRR_CTL_VRR_ENABLE |
trans_vrr_ctl(crtc_state));
- }
- }
-
if (crtc_state->vrr.dc_balance.enable) {
intel_de_write(display,
TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
@@ -675,6 +663,12 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
crtc_state->vrr.dc_balance.vblank_target);
}
+
+ ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+ if (crtc_state->cmrr.enable)
+ ctl |= VRR_CTL_CMRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -683,10 +677,17 @@ void intel_vrr_disable(const struct intel_crtc_state
*old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
+ u32 ctl;
if (!old_crtc_state->vrr.enable)
return;
+ ctl = trans_vrr_ctl(old_crtc_state);
+ if (intel_vrr_always_use_vrr_tg(display))
+ ctl |= VRR_CTL_VRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
if (old_crtc_state->vrr.dc_balance.enable) {
intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
@@ -702,8 +703,6 @@ void intel_vrr_disable(const struct intel_crtc_state
*old_crtc_state)
}
if (!intel_vrr_always_use_vrr_tg(display)) {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- trans_vrr_ctl(old_crtc_state));
intel_de_wait_for_clear(display,
TRANS_VRR_STATUS(display,
cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
--
2.48.1
