Add function to check if DC Balance possibile on
requested PIPE and also validate along with DISPLAY_VER
check.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 98d305d02f35..8d7d19b86376 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -256,6 +256,22 @@ void intel_vrr_compute_cmrr_timings(struct
intel_crtc_state *crtc_state)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+static
+int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+ * FIXME: Currently Firmware supports DC Balancing on PIPE A
+ * and PIPE B. Account those limitation while computing DC
+ * Balance parameters.
+ */
+ return (HAS_VRR_DC_BALANCE(display) &&
+ ((pipe == PIPE_A) || (pipe == PIPE_B)));
+}
+
static
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
--
2.48.1
