On Wed, 29 Jan 2025, Imre Deak <imre.d...@intel.com> wrote:
> From: Imre Deak <imre.d...@gmail.com>
>
> Align the DDI_BUF_CTL register flag definitions with how this is done
> elsewhere.
>
> Signed-off-by: Imre Deak <imre.d...@gmail.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7fe4e71fc08ec..5cee6a96270af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3621,27 +3621,29 @@ enum skl_power_gate {
> #define _DDI_BUF_CTL_B 0x64100
> /* Known as DDI_CTL_DE in MTL+ */
> #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
> -#define DDI_BUF_CTL_ENABLE (1 << 31)
> +#define DDI_BUF_CTL_ENABLE REG_BIT(31)
> #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
> #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
> -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
> -#define DDI_BUF_EMP_MASK (0xf << 24)
> -#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
> +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
> +#define DDI_BUF_TRANS_SELECT(n)
> REG_FIELD_PREP(DDI_BUF_EMP_MASK, n)
> +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20)
> +#define DDI_BUF_PHY_LINK_RATE(r)
> REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, r)
Ville has been advocating wrapping macro arguments in parens also in
these cases, and I'm starting to lean that way too.
Other than that,
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
> #define DDI_BUF_PORT_DATA_10BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
> #define DDI_BUF_PORT_DATA_20BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
> #define DDI_BUF_PORT_DATA_40BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
> -#define DDI_BUF_PORT_REVERSAL (1 << 16)
> +#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
> #define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
> #define DDI_BUF_LANE_STAGGER_DELAY(symbols)
> REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
> symbols)
> -#define DDI_BUF_IS_IDLE (1 << 7)
> +#define DDI_BUF_IS_IDLE REG_BIT(7)
> #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
> -#define DDI_A_4_LANES (1 << 4)
> -#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 :
> ((width) - 1)) << 1)
> -#define DDI_PORT_WIDTH_MASK (7 << 1)
> +#define DDI_A_4_LANES REG_BIT(4)
> +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
> + (width) == 3 ? 4
> : (width) - 1)
> #define DDI_PORT_WIDTH_SHIFT 1
> -#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
> +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
>
> /* DDI Buffer Translations */
> #define _DDI_BUF_TRANS_A 0x64E00
--
Jani Nikula, Intel
