On Wed, Dec 07, 2016 at 07:28:12PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > BSpec says: > "Overlay Clock Gating Must be Disabled: Overlay & L2 Cache clock gating > must be disabled in order to prevent device hangs when turning off overlay.SW > must turn off Ovrunit clock gating (6200h) and L2 Cache clock gating (C8h)." > > We only turned off the overlay clock gating (due to lack of docs I > presume). After a bit of experimentation it looks like the the magic > C8h register lives in the PCI config space of device 0, and the magic > bit appears to be bit 2. Or at the very least this eliminates the GPU > death after MI_OVERLAY_OFF. > > L2 clock gating seems to save ~80mW, so let's keep it on unless we need > to actually use the overlay. > > Also let's move the OVRUNIT clock gating to the same place since we can, > and 845 supposedly doesn't need it. > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Acked-by: Chris Wilson <ch...@chris-wilson.co.uk> -Chris
-- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
