> how do I know that my literal pool is actively > cached at execution of a certain instruction?
Short answer: you cannot. Long answer: Keep your data in a 256-byte-aligned area separate from your instructions. If you are really fussy, separate read-only from read/write data in separate 256-byte-aligned areas. Separate into another area any data that is modified by one task and read or written by another. This will give you a fighting chance that your data will be in cache. If my hypothetical L R0,=F'1' were shortly preceded by L R2,=F'2' then there is a good chance that the F'1' will already be in cache when you get to the L R0. (A good example but poor coding practice! Use LHI R0,1 not L R0,=F'1' and avoid data cache issues altogether.) Really long answer: The hardware keeps track. There is a set of counters for cache hits and misses of various types. The counters are model-dependent. Take a look at SMF 113 and go from there. (Products like Omegamon and MainView may have the ability to report on the counters -- I don't know.) Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Brian Chapman Sent: Tuesday, August 13, 2019 7:26 AM To: [email protected] Subject: Re: Instruction speeds Thanks everyone for your input. I learned a lot from these responses. I actually meant to write ADD HALFWORD IMMEDIATE in my original email. I was surprised to hear about LA. I had assumed that direct register manipulation was the fastest. On the topic of cache, how do I know that my literal pool is actively cached at execution of a certain instruction? What would cause the hardware to move my literal pool out of cache? ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
