On Mon, 4 Apr 2016 09:30:47 -0700, Greg Dyck wrote: > >1) ... >The results of one instruction are placed in storage after the results >of all preceding instructions have been placed in storage and before >any results of the succeeding instructions are stored, as observed by >other CPUs and by channel programs. The results of any one instruction >are stored in the sequence specified for that instruction. > >2) ... > >3) ... > >All interruptions and the execution of certain instructions cause a >serialization of CPU operations. A serialization operation consists in >completing all conceptually previous storage accesses by the CPU, as >observed by other CPUs and by channel programs, before the conceptually >subsequent storage accesses occur. Serialization affects the sequence >of all CPU accesses to storage and to the storage keys, except for those >associated with ART-table-entry and DAT-table-entry fetching. > What does rule 3 require that isn't equallly implied by rule 1? (Or did I trim too much?)
What does this imply about register accesses? Does the STM early in the FLIH observe register accesses "conceptually" serialized as storage accesses are? -- gil ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
