According to this chart, bit 32 should remain U (for unchanged?) even in 31 bit
mode.
But then again, it should also remain U for BASR.
Actually, I have no idea how to read this chart.
| | | | Address | Branch or | | |
|
| | | | Placed in GR R1 |2nd-Op Adr.| |
| |
| | | |_____ _____ _____ _____|_____ _____| R2 | PSW
| PSW |
| | | In |Bits | Bit |Bits | Bit |Bits |Bits | Bit |Bit 31
|Bit 32 |
|Instruction| Format |Mode |0-31 | 32 |33-62| 63 |0-32 |33-63| 63 |Set to
|Set to |
|___________|________|_____|_____|_____|_____|_____|_____|_____|_____|_______|_______|
| BALR*/BAL | RR/RX | 24 | U | *** | *** | IA | SIA | SIA |LSExc| U
| U |
| | | | | | | | | | |
| |
| | | 31 | U | BAM | IA | IA | SIA | SIA |LSExc| U
| U |
| | | | | | | | | | |
| |
| | | 64 | IA | IA | IA | IA | SIA | SIA |LSExc| U
| U |
| | | | | | | | | | |
| |
|BASR*/BAS/ | RR/RX/ |24/31| U | BAM | IA | IA | SIA | SIA |LSExc| U
| U |
|BRAS/BRASL | RI/RIL | | | | | | | | |
| |
| | | 64 | IA | IA | IA | IA | SIA | SIA |LSExc| U
| U |
| | | | | | | | | | |
| |
| BASSM* | RR |24/31| U | BAM | IA | IA | SIA | SIA | 0 | 0
| R232 |
| | | | | | | | | | |
| |
| | |24/31| U | BAM | IA | IA | SIA | SIA | 1G0 | 1
| 1 |
| | | | | | | | | | |
| |
| | | 64 | IA | IA | IA | 1 | SIA | SIA | 0 | 0
| R232 |
| | | | | | | | | | |
| |
| | | 64 | IA | IA | IA | 1 | SIA | SIA | 1G0 | 1
| 1 |
| | | | | | | | | | |
| |
| BSM** | RR |24/31| U | BAM | U | U | SIA | SIA | 0 | 0
| R232 |
| | | | | | | | | | |
| |
| | |24/31| U | BAM | U | U | SIA | SIA | 1G0 | 1
| 1 |
| | | | | | | | | | |
| |
| | | 64 | U | U | U | 1 | SIA | SIA | 0 | 0
| R232 |
| | | | | | | | | | |
| |
| | | 64 | U | U | U | 1 | SIA | SIA | 1G0 | 1
| 1 |
| | | | | | | | | | |
| |
|BCTR*/BCT/ | RR/RX/ |24/31| NLA | NLA | NLA | NLA | SIA | SIA |LSExc| U
| U |
|BCTGR*/BCTG| RRE/RXE| | | | | | | | |
| |
| | | 64 | NLA | NLA | NLA | NLA | SIA | SIA |LSExc| U
| U |
| | | | | | | | | | |
| |
| LA/LAE | RX/RX |24/31| U | 0 |Op2Ad|Op2Ad| FZ | SR1 | 0/1 | U
| U |
| | | | | | | | | | |
| |
| | | 64 |Op2Ad|Op2Ad|Op2Ad|Op2Ad| SR1 | SR1 | 0/1 | U
| U |
|___________|________|_____|_____|_____|_____|_____|_____|_____|_____|_______|_______|
________________________________________________________________________
|Explanation: |
| |
| - The address does not exist, or the bit has no special effect. |
| |
| * The action associated with the R2 field is not performed if the |
| field is zero. |
| |
| ** The action associated with the R1 or R2 field is not performed |
| if the field is zero. |
| |
| *** The instruction-length code, condition code, and program mask |
| are saved in bit positions 32-39 of the link address, and bits |
| 40-63 of the updated instruction address are saved in bit |
| positions 40-63. |
| |
| 0/1 Bit 63 can be zero or one. |
| |
| 1G0 Bit 63 is one and is left one, but the branch address is |
| generated as if the bit is zero. |
| |
| BAM Bit 32 of the link address is set with the basic-addressing-mode|
| bit, bit 32 of the PSW. |
| |
| FZ Bits 0-32 of the second-operand address are forced to zeros in |
| the 24-bit or 31-bit addressing mode. |
| |
| IA Bits of the link address are set with the updated instruction |
| address as shown. |
| |
| LSExc A late specification exception is recognized if the bit is one. |
| |
| NLA The instruction does not produce a link address. (The |
| instruction is shown simply as an example of a non-linkage |
| branch instruction.) |
| |
| Op2Ad Bits of the address in general register R1 are set with the |
| corresponding bits of the second-operand address as shown. |
| |
| R232 The basic-addressing-mode bit, bit 32 of the PSW, is set with |
| bit 32 of general register R2. |
| |
| SIA Bits 0-63 of the branch address are used to set the instruction |
| address in the PSW. Bits 0-39 of the branch address are forced |
| to zeros in the 24-bit addressing mode. Bits 0-32 are forced to|
| zeros in the 31-bit addressing mode. |
| |
| SR1 Bits of the second-operand address are used to set the |
| corresponding bits of the address in the R1 general register as |
| shown. Bits 0-39 of the second-operand address are forced to |
| zeros in the 24-bit addressing mode. Bits 0-32 are forced to |
| zeros in the 31-bit addressing mode. |
| |
| U Unchanged. |
|________________________________________________________________________|
Figure 5-2. Summary of Simple Branch Linkage Instructions and Other
Instructions
-----Original Message-----
From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of
Micheal Butz
Sent: Friday, April 29, 2011 3:45 PM
To: [email protected]
Subject: Re: Strange BALR 31 bit mode experince
But BALR didn't update high order bit if R1 in 31 bit mode
Sent from my iPhone
On Apr 29, 2011, at 3:35 PM, "Barkow, Eileen" <[email protected]>
wrote:
> From principles of operation:
>
> Both BRANCH AND LINK and BRANCH AND SAVE have an R1 field. They form
> a branch address by means of fields that depend on the instruction.
> The operations of the instructions are summarized as follows:
> In the 24-bit addressing mode, both instructions place the return
> address in bit positions 40-63 of general register R1 and leave bits
> 0-31 of that register unchanged. BRANCH AND LINK places the
> instruction-length code for the instruction and also the condition
> code and program mask from the current PSW in bit positions 32-39 of
> general register R1. BRANCH AND SAVE places zeros in those bit
> positions.
> In the 31-bit addressing mode, both instructions place the return
> address in bit positions 33-63 and a one in bit position 32 of
> general register R1, and they leave bits 0-31 of the register
> unchanged.
> In the 64-bit addressing mode, both instructions place the return
> address in bit positions 0-63 of general register R1.
> In any addressing mode, both instructions generate the branch
> address under the control of the current addressing mode. The
> instructions place bits 0-63 of the branch address in bit positions
> 64-127 of the PSW. In the RR format, both instructions do not
> perform branching if the R2 field of the instruction is zero.
>
> -----Original Message-----
> From: IBM Mainframe Discussion List [mailto:[email protected]] On
> Behalf Of Ivan Warren
> Sent: Friday, April 29, 2011 3:30 PM
> To: [email protected]
> Subject: Re: Strange BALR 31 bit mode experince
>
> On 4/29/2011 9:21 PM, Micheal Butz wrote:
>> Yes changed it still should of worked
>>
>> IVAN would of worked on Hercules
>>
>
> Oh Believe me..
>
> BALR works the same on hercules as it does on other implementations of
> the S/370, S/390 and z/Architecture !
>
> --Ivan
>
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