>From principles of operation:

Both BRANCH AND LINK and BRANCH AND SAVE have an R1 field. They form a branch 
address by means of fields that depend on the instruction. The operations of 
the instructions are summarized as follows:  
In the 24-bit addressing mode, both instructions place the return address in 
bit positions 40-63 of general register R1 and leave bits 0-31 of that register 
unchanged. BRANCH AND LINK places the instruction-length code for the 
instruction and also the condition code and program mask from the current PSW 
in bit positions 32-39 of general register R1. BRANCH AND SAVE places zeros in 
those bit positions.  
In the 31-bit addressing mode, both instructions place the return address in 
bit positions 33-63 and a one in bit position 32 of general register R1, and 
they leave bits 0-31 of the register unchanged.  
In the 64-bit addressing mode, both instructions place the return address in 
bit positions 0-63 of general register R1.  
In any addressing mode, both instructions generate the branch address under the 
control of the current addressing mode. The instructions place bits 0-63 of the 
branch address in bit positions 64-127 of the PSW. In the RR format, both 
instructions do not perform branching if the R2 field of the instruction is 
zero.

-----Original Message-----
From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of 
Ivan Warren
Sent: Friday, April 29, 2011 3:30 PM
To: [email protected]
Subject: Re: Strange BALR 31 bit mode experince

On 4/29/2011 9:21 PM, Micheal Butz wrote:
> Yes changed it still should of worked
>
> IVAN would of worked on Hercules
>

Oh Believe me..

BALR works the same on hercules as it does on other implementations of 
the S/370, S/390 and z/Architecture !

--Ivan

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