On 2019-08-30 06:24, Brian J. Murrell wrote:
I am trying to override a target that has a general definition in an
included Makefile with a more specific one. But it seems that the
override only happens if the overriding target has a recipe?
Overriding targets isn't a concept in make; it can happen by mistake
and is diagnosed as such.
I.e:
Makefile.mk:
1 foo.gz:
2 echo "foo" | gzip > $@
Makefile:
1 include Makefile.mk
2
3 %.gz: %
4 rm -f $@
5 gzip $<
6
7 foo:
8 echo "better foo" > $@
9
10 foo.gz: foo
This rule without a recipe is a make feature; what it does
is specify that foo.gz depends on foo. This can add additional
dependencies to an existing target.
My expectation is that the foo.gz target on line 10 of Makefile
overrides the one on line 1 of Makefile.mk, but it doesn't unless I
make it:
There is in fact a form of overriding going on, just not
the one you want.
Your build system specifies two conflicting rules: a pattern rule
that converts any % to %.gz, and a diect rule for
updating the specific file foo.gz.
That specific rule for foo.gz is, effectively, an override
for the general pattern rule.
Thus if we want foo.gz to be updated using the pattern rule,
then what we need is for the direct rule not to exist at all.
We need a mechanism for deleting a rule (no such feature) or else
we must structure the code so that we can conditionally prevent
a rule from being defined.
For instance:
# Makefile.mk
ifeq ($(DEFINED_foo.gz),)
foo.gz:
[..commands..]
DEFINED_foo.gz = y
endif
Now in Makefile we can suppress the definition by defining
that variable:
# Makefile
DEFINED_foo.gz := y
include Makefile.mk
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