Yes, this is documented behavior. A target can be mentioned multiple times
but only one mention can provide a recipe. Others simply add to the prereq
list. Thus:
foo.gz: abc
foo.gz: def
foo.gz: ghi
<recipe>
Has 3 prerequisite files. This behavior is documented, baked in, and is not
going to change. And is considered a feature.
There's no way to suppress the warning AFAIK but there are various
workarounds such as putting the recipe in a variable:
recipe = echo Building $@
foo.gz:
@$(recipe)
Changing the value of the variable will not trigger a warning. You could
also look into double-colon rules, and if you really want to go for it
almost anything can be done with $(eval ...).
David
On Fri, Aug 30, 2019 at 8:08 AM Brian J. Murrell <br...@interlinx.bc.ca>
wrote:
> I am trying to override a target that has a general definition in an
> included Makefile with a more specific one. But it seems that the
> override only happens if the overriding target has a recipe?
>
> I.e:
>
> Makefile.mk:
> 1 foo.gz:
> 2 echo "foo" | gzip > $@
>
> Makefile:
> 1 include Makefile.mk
> 2
> 3 %.gz: %
> 4 rm -f $@
> 5 gzip $<
> 6
> 7 foo:
> 8 echo "better foo" > $@
> 9
> 10 foo.gz: foo
>
> My expectation is that the foo.gz target on line 10 of Makefile
> overrides the one on line 1 of Makefile.mk, but it doesn't unless I
> make it:
>
> foo.gz: foo
> rm -f $@
> gzip $<
>
> by redundantly adding the %.gz: % recipe to it.
>
> Is this intended behaviour?
>
> Also, is there a way to suppores of the "warning: overriding recipe for
> target" messages that make emits? I realize they can be useful when
> you inadvertently override a target, but it would be nice to indicate
> in the Makefile that you understand you are overriding a target and
> don't want the warning.
>
> Cheers,
> b.
>
> _______________________________________________
> Help-make mailing list
> Help-make@gnu.org
> https://lists.gnu.org/mailman/listinfo/help-make
>
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