On Mon, 2015-07-27 at 17:44 -0500, Larry Evans wrote:
> > Are you trying to compile the same file with different compilers, or
> > something?
> >
> Yes.
>
> The attached Makefile summarizes methods tried and the reason
> they failed or succeeded. The last method, the one with
> target=compiles.def, uses define..endef and succeeds.
It's very odd from a make standpoint to be building lots of targets,
with the same name, with different tools, in the same rule. That's just
not how make is designed to work.
Make is designed to create multiple targets from multiple prerequisites
and that's how it "loops", not with a for loop or a traditional
procedural programming construct.
So, something like this:
COMPILERS = gcc clang
compile-all: $(addprefix main.,$(COMPILERS))
main.% : main.%.o
$(COMPILER.$*) -o $@ $^
main.%.o : main.c
$(COMPILER.$*) -c -o $@ $<
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