On Mon, 2015-07-27 at 13:50 -0500, Larry Evans wrote: > Thanks Paul. It works; however, what I really > want is to use the compiler to compile a source file to > and object file.
Well, it usually works best to ask the question you want the answer to, rather than a different question :-). > How should I modify this 2nd version of the Makefile to make it compile > to produce the .o and not the a.out file? BTW, I'd rather not > hardcode the -c into compile command because the actual args to the > compile command depend on the compiler. Also, I'd like the output > object file name to be $(MAIN).gcc.o instead of just $(MAIN).o. I don't really understand this, at all. Why do you have a loop in your recipe? Can you provide a more realistic example? Or else maybe provide some higher-level explanation of what you're trying to do? In your original question I thought maybe you have multiple compilers and you wanted to write a "show info" type rule to show the paths to all of them. But in this version of the makefile you're actually trying to compile code, so I don't understand why you're trying to loop through multiple compilers...? Are you trying to compile the same file with different compilers, or something? _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make
