Hi Jason, I'm asking can we read the registers (for example esp or cr3 etc..) while executing cache miss handler using packet object. Have a look at this <https://www.mail-archive.com/[email protected]/msg09981.html> post. In that one, he read the contents of esp. Is it the correct way to access registers if we have the packet object? Or are there other ways to access regs using packet object?
Thank you, Abhijith Pogiri. On Tue 28 Apr, 2020, 8:28 AM svk V, <[email protected]> wrote: > Hello Jason > Is it possible to find ThreadID (Hardware Thread ID) of a cache block? > In the request object only contextID and masterID are present. > > Thanks > Sai > > On Tue, Apr 28, 2020 at 12:00 AM Jason Lowe-Power via gem5-users < > [email protected]> wrote: > >> Hi Abhijith, >> >> I'm not sure exactly what you're asking here. However, the request object >> (in the packet) should have a masterID which refers to the original >> requestor. You can use `system->lookupMasterId` to get the SimObject that >> created that request. >> >> Cheers, >> Jason >> >> On Mon, Apr 27, 2020 at 5:47 AM POGIRI VENKATA NARAYANA ABHIJITH cs16b018 >> via gem5-users <[email protected]> wrote: >> >>> If a load misses processors' private cache (assuming there are 2 levels >>> of cache), then inside that miss handler function, is there a way to >>> access thread_context of the process in order to read the required register? >>> >>> Thank you, >>> Abhijith Pogiri. >>> _______________________________________________ >>> gem5-users mailing list -- [email protected] >>> To unsubscribe send an email to [email protected] >>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >> >> _______________________________________________ >> gem5-users mailing list -- [email protected] >> To unsubscribe send an email to [email protected] >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > >
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