[gem5-users] How to access registers while processing cache miss?

[POGIRI VENKATA NARAYANA ABHIJITH cs16b018 via gem5-users]

If a load misses processors' private cache (assuming there are 2 levels of
cache),  then inside that miss handler function, is there a way to access
thread_context of the process in order to read the required register?

Thank you,
Abhijith Pogiri.

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