[gem5-users] Re: How to access registers while processing cache miss?

[Jason Lowe-Power via gem5-users]

Hi  Abhijith,

I'm not sure exactly what you're asking here. However, the request object
(in the packet) should have a masterID which refers to the original
requestor. You can use `system->lookupMasterId` to get the SimObject that
created that request.

Cheers,
Jason

On Mon, Apr 27, 2020 at 5:47 AM POGIRI VENKATA NARAYANA ABHIJITH cs16b018
via gem5-users <gem5-users@gem5.org> wrote:

> If a load misses processors' private cache (assuming there are 2 levels of
> cache),  then inside that miss handler function, is there a way to access
> thread_context of the process in order to read the required register?
>
> Thank you,
> Abhijith Pogiri.
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