Just to access physical addresses by commMonitor, I have modified "configs/common/CacheConfig.py" as Patrick indicated and used below command:
build/ARM/gem5.opt --debug-flag=CommMonitor --debug-file=trace.out.gz configs/example/se.py -c tests/test-progs/hello/bin/arm/linux/hellocpu-type=timing then I the terminal prompted following error: system.monitor2 = CommMonitor(trace_file = "trace2.txt") NameError: name 'CommMonitor' is not defined then I read this https://www.mail-archive.com/gem5-users%40gem5.org/msg08610.html (which is not completely answered) And I also added these lines to "configs/common/CacheConfig.py": from m5.util import addToPath, fatal addToPath('../../src/mem') from CommMonitor import CommMonitor I got this: gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Oct 18 2014 20:14:39 gem5 started Oct 29 2014 10:40:21 gem5 executing on KeepChange command line: build/ARM/gem5.opt --debug-flag=CommMonitor --debug-file=trace.out.gz configs/example/se.py --caches --l2cache --l2_size=2MB --cpu-type=timing --mem-type=DDR3_1600_x64 -c tests/test-progs/hello/bin/arm/linux/hello /home/farshid/gem5-stable/configs/common/CacheConfig.py:55: SyntaxWarning: import * only allowed at module level def config_cache(options, system): Traceback (most recent call last): File "<string>", line 1, in <module> File "/home/farshid/gem5-stable/src/python/m5/main.py", line 388, in main exec filecode in scope File "configs/example/se.py", line 60, in <module> import CacheConfig File "/home/farshid/gem5-stable/configs/common/CacheConfig.py", line 51, in <module> from CommMonitor import CommMonitor File "/home/farshid/gem5-stable/src/mem/CommMonitor.py", line 41, in <module> from MemObject import MemObject File "/home/farshid/gem5-stable/src/mem/MemObject.py", line 33, in <module> from ClockedObject import ClockedObject ImportError: No module named ClockedObject any clue? Thanks On Mon, Oct 20, 2014 at 11:07 PM, Farshid Hajhashemi < [email protected]> wrote: > Thanks of both you guys for your gentle responses > Yes, I need address and also data. > I had a look in packet.hh and data pointer but don't know how to make it > appear on commMonitor trace. > I'v tried to understand the whole concept of how to modify files in gem5 > but this is so new for me and every detailed description would appreciated. > > Thanks again > On Oct 20, 2014 10:50 PM, "Patrick L. via gem5-users" < > [email protected]> wrote: > >> Andreas Hansson via gem5-users <gem5-users <at> gem5.org> writes: >> >> > >> > Hi guys, >> > >> > At this point, the CommMonitor does not output the data in the trace. >> In >> > most cases this is fine, but it sounds like you actually want to dig >> > through the data itself Farshid? >> > >> > If so, you would need to edits the src/proto/packet.proto and add an >> > appropriate field, and then do the corresponding memcpy in the >> CommMonitor >> > where the trace is generated. Beware that this will significantly >> bloat >> > the traces though. >> > >> > Andreas >> > >> > On 20/10/2014 18:55, "Patrick L. via gem5-users" <gem5-users <at> >> gem5.org> >> > wrote: >> > >> > >Farshid Hajhashemi via gem5-users <gem5-users <at> gem5.org> writes: >> > > >> > >> >> > >> HelloI need to profile all accesses to physical memory(DRAM) >> including >> > >address and data. >> > >> I did scons for ARM architecture in SE mode; is there any clue >> where & >> > >how I should add my listeners? >> > >> >> > >> Best Regards >> > >> Farshid Hajhashemi >> > >> >> > >> >> > >> >> > >> >> > >> >> > >> _______________________________________________ >> > >> gem5-users mailing list >> > >> gem5-users <at> gem5.org >> > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > >> > >Farshid, >> > > >> > >One way is to modify the file configs/common/CacheConfig.py. Comment >> out >> > >these lines: >> > > >> > > #system.l2.cpu_side = system.tol2bus.master >> > > #system.l2.mem_side = system.membus.slave >> > > >> > >And add these lines: >> > > >> > > system.monitor2 = >> > >CommMonitor(trace_file="CT_mon2.trc",trace_enable=True) >> > > >> > > system.monitor2.slave = system.l2.mem_side >> > > system.membus.slave = system.monitor2.master >> > > system.l2.cpu_side = system.tol2bus.master >> > > >> > >In the default CPU mode, it won't log the accesses. One way to remedy >> > >this is to run in timing mode, with the "cpu-type=timing" option on >> the >> > >command line. If you are using the modifications I gave above, you >> also >> > >need to enable the L2 with the "l2cache" option. >> > > >> > >Regards, >> > >Patrick La Fratta >> > > >> > >_______________________________________________ >> > >gem5-users mailing list >> > >gem5-users <at> gem5.org >> > >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > >> >> Thanks for the correction, Andreas. I haven't been examining data, so I >> was making the assumption that the PacketPtr that the CommMonitor >> examines would provide easy access to the data. Looks like I may have >> been mistaken. >> >> Looking in src/mem/packet.hh, it does appear that the Packet class has >> an accessor named "getPtr" that provides access to a member named >> "data." It looks like this might be a means for CommMonitor to examine >> the data in a packet, but I would not be surprised if I am missing an >> important detail somewhere. >> >> Regards, >> Patrick >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
