Hi guys,

At this point, the CommMonitor does not output the data in the trace. In
most cases this is fine, but it sounds like you actually want to dig
through the data itself Farshid?

If so, you would need to edits the src/proto/packet.proto and add an
appropriate field, and then do the corresponding memcpy in the CommMonitor
where the trace is generated. Beware that this will significantly bloat
the traces though.

Andreas

On 20/10/2014 18:55, "Patrick L. via gem5-users" <[email protected]>
wrote:

>Farshid Hajhashemi via gem5-users <gem5-users <at> gem5.org> writes:
>
>>
>> HelloI need to profile all accesses to physical memory(DRAM) including
>address and data.
>> I did scons for ARM architecture in SE mode; is there any clue where &
>how I should add my listeners?
>>
>> Best Regards
>> Farshid Hajhashemi
>>
>>
>>
>>
>>
>> _______________________________________________
>> gem5-users mailing list
>> gem5-users <at> gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Farshid,
>
>One way is to modify the file configs/common/CacheConfig.py. Comment out
>these lines:
>
>        #system.l2.cpu_side = system.tol2bus.master
>        #system.l2.mem_side = system.membus.slave
>
>And add these lines:
>
>        system.monitor2 =
>CommMonitor(trace_file="CT_mon2.trc",trace_enable=True)
>
>        system.monitor2.slave = system.l2.mem_side
>        system.membus.slave = system.monitor2.master
>        system.l2.cpu_side = system.tol2bus.master
>
>In the default CPU mode, it won't log the accesses. One way to remedy
>this is to run in timing mode, with the "cpu-type=timing" option on the
>command line. If you are using the modifications I gave above, you also
>need to enable the L2 with the "l2cache" option.
>
>Regards,
>Patrick La Fratta
>
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>[email protected]
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