Farshid Hajhashemi via gem5-users <gem5-users <at> gem5.org> writes:
> > HelloI need to profile all accesses to physical memory(DRAM) including address and data. > I did scons for ARM architecture in SE mode; is there any clue where & how I should add my listeners? > > Best Regards > Farshid Hajhashemi > > > > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users Farshid, One way is to modify the file configs/common/CacheConfig.py. Comment out these lines: #system.l2.cpu_side = system.tol2bus.master #system.l2.mem_side = system.membus.slave And add these lines: system.monitor2 = CommMonitor(trace_file="CT_mon2.trc",trace_enable=True) system.monitor2.slave = system.l2.mem_side system.membus.slave = system.monitor2.master system.l2.cpu_side = system.tol2bus.master In the default CPU mode, it won't log the accesses. One way to remedy this is to run in timing mode, with the "cpu-type=timing" option on the command line. If you are using the modifications I gave above, you also need to enable the L2 with the "l2cache" option. Regards, Patrick La Fratta _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
