Hi, you need to properly order the lock acquisition with the counter manipulations, for example as below (or see http://lxr.free-electrons.com/source/arch/arm/include/asm/spinlock.h or http://blogs.arm.com/software-enablement/188-locks-swps-and-two-smoking-barriers-part-2/ )
On Monday 07 October 2013 02:54:08 GE ZHIGUO wrote: > The disassembly codes of the spin_lock are like follows: > > LDREX r1, [r0] Option 1) Use an LDAEX here (but is a v8 thing) > CMP r1, #0 > BNE RELOAD > STREX r2, r3, [r0] > CMP r2, #0 > BNE RELOAD Option 2) (v7) Use a DMB here. > B LOCK_SUCCESSFUL ... Freeing the lock: Option 1) (v8) Use STL to free the lock Option 2) (v7) Use a DMB here, and then store. [...] > I set each CPU does about 10000 iterations and the final value of the > counter should be 20000, however, The actual number is not 20000, but > around 19999, or 19997. Can you please re-test with the changes suggested above? (v7 for now in Gem5). > I debugged and found that in some cases, two CPUs can obtain the mutex > simultaneously and both CPUs enter the critical section. That should not happen, regardless of the counter breakage. How did you debug this? Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
