Hello, Please forgive me if I am TOTALLY new to the concept of architecture simulation. At this stage I am trying to get the picture by building and playing with the pre-compiled images.
What i want: I saw in the latest presentation in the tutorial part og gem5 wiki, the developers have set up the system to run angry birds on Android over ARM processor. That is what i want to do now. what I have done so far: from "BBench-gem5" part of the wiki, I followed "Running BBench on Android with gem5" section and I got the following on my ubuntu-32 bit os terminal. Am I in the right track? what should i do next? thank you: vahid@vahid-ThinkPad-T420:~/gem5$ build/ARM/m5.debug configs/example/fs.py -b bbench-gb --kernel=vmlinux.smp.mouse.arm gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Aug 23 2012 10:03:32 gem5 started Aug 24 2012 15:37:05 gem5 executing on vahid-ThinkPad-T420 command line: build/ARM/m5.debug configs/example/fs.py -b bbench-gb --kernel=vmlinux.smp.mouse.arm Global frequency set at 1000000000000 ticks per second info: kernel located at: /home/vahid/gem5/system/binaries/vmlinux.smp.mouse.arm Listening for system connection on port 5900 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 info: Using bootloader at address 0x80000000 **** REAL SIMULATION **** info: Entering event queue @ 0. Starting simulation... warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: The ccsidr register isn't implemented and always reads as 0. warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented
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