On Mon, Jul 13, 2020 at 9:40 AM Florian Weimer <fwei...@redhat.com> wrote:
>
> * Richard Biener:
>
> >> Looks good. I like it.
> >
> > Likewise. Btw, did you check that VIA family chips slot into Level A
> > at least?
>
> Those seem to lack SSE4.2, so they land in the baseline.
>
> > Where do AMD bdverN slot in?
>
> bdver1 to bdver3 (as defined by GCC) should land in Level B (so Level A
> if that is dropped). bdver4 and znver1 (and later) should land in
> Level C.
>
> >> My only concerns are
> >>
> >> 1. Names like “x86-100”, “x86-101”, what features do they support?
> >
> > Indeed I didn't get the -100, -101 part. On the GCC side I'd have
> > suggested -march=generic-{A,B,C,D} implying the respective
> > -mtune.
>
> With literal A, B, C, D, or are they just placeholders? If not literal
> levels, then what we should use there?
>
> I like the simplicity of numbers. I used letters in the proposal to
> avoid confusion if we alter the proposal by dropping or levels, shifting
> the meaning of those that come later. I expect to switch back to
> numbers again for the final version.
They are indeed placeholders though I somehow prefer letters to
numbers. But this is really bike-shedding territory. Good documentation
on the tools side will be more imporant as well as consistent spelling
between tools sets, possibly driven by a good choice from within the
psABI document.
Richard.
