Hi Segher,
> I'll need some compilable source code to investigate this. That means
> compilable for*me*, so with some target that is in trunk.
I'm not sure I can trigger this on trunk. I've attached a minimal patch, which
adds a pattern which can trigger the behaviour, and 2 c files: foo.c matches a
similar pattern which *can* be combined, bar.c should match the added pattern,
but does not. I believe it is due to some register equivalence problem.
> What you want isn't the kind of optimisation combine does at all. You
> probably want to look at something like cprop; or look at how this
> code is generated, that doesn't seem optimal.
foo.c is a very similar case handled by combine, and bar.c can be handled if
the predicate checking that it is a const_vector is removed, which makes me
think it is a register equivalence issue.
from foo.c.263r.combine:
Trying 11 -> 12:
11: r97:V4SF=r96:V4SF*const_vector
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
12: r99:V4SI=fix(unspec[r97:V4SF] 25)
REG_DEAD r97:V4SF
Successfully matched this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (reg:V4SF 96 [ D.3422 ])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3])
repeated x4
]))
] UNSPEC_FRINTZ)))
from bar.c.263r.combine:
Trying 10 -> 12:
10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
Failed to match this instruction:
(set (reg:V4SF 98 [ D.3424 ])
(mult:V4SF (float:V4SF (reg:V4SI 96 [ D.3422 ]))
(reg:V4SF 99)))
I would expect combine to try this pattern:
(set (reg:V4SF 98 [ D.3424 ])
(mult:V4SF (float:V4SF (reg:V4SI 96 [ D.3422 ]))
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
])))
but it does not.
In both cases the constant vector is set outside the basic block, but in the
'foo' case, combine successfully matches the pattern using register
equivalence, while in the 'bar' case in does not.
testcases compiled with:
aarch64-none-elf-gcc -S -mcpu=cortex-a53 -O2 -ftree-vectorize -fno-inline
-fdump-rtl-all -fno-vect-cost-model -dp -fdump-rtl-combine-all
-fdump-tree-optimized -o - [foo.c/bar.c]
$gcc -v
COLLECT_GCC=$INSTALL/bin/aarch64-none-elf-gcc
COLLECT_LTO_WRAPPER=$INSTALL/libexec/gcc/aarch64-none-elf/10.0.0/lto-wrapper
Target: aarch64-none-elf
Configured with: src/gcc/configure --target=aarch64-none-elf --prefix=$INSTALL/
--with-gmp=$BUILD/host-tools --with-mpfr=$BUILD/host-tools
--with-mpc=$BUILD/host-tools --with-isl=$BUILD/host-tools --disable-shared
--disable-nls --disable-threads --disable-tls --enable-checking=yes
--enable-languages=c,c++,fortran --with-newlib --with-pkgversion=unknown
Thread model: single
gcc version 10.0.0 20190612 (experimental) (unknown)
From 7e744509575030ca5b3fa6042d02d27171fbfbfd Mon Sep 17 00:00:00 2001
From: Joel Hutton <joel.hut...@arm.com>
Date: Tue, 11 Jun 2019 10:10:07 +0100
Subject: [PATCH] Minimal pattern to demonstrate combine behaviour
---
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-simd.md | 13 +++++++++++++
gcc/config/aarch64/aarch64.c | 6 ++++++
gcc/config/aarch64/predicates.md | 3 +++
4 files changed, 23 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index a0723266f22..ff1787c37ed 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -483,6 +483,7 @@ enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
enum reg_class aarch64_regno_regclass (unsigned);
int aarch64_asm_preferred_eh_data_format (int, int);
int aarch64_fpconst_pow_of_2 (rtx);
+int aarch64_fp_const_vec (rtx);
machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
machine_mode);
int aarch64_uxt_size (int, HOST_WIDE_INT);
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index d4c48d2aa61..698b49c006f 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2133,6 +2133,19 @@
"TARGET_SIMD"
{})
+(define_insn "*aarch64_combine_scvtf"
+ [(set (match_operand 0 "register_operand" "=w")
+ (mult
+ (float
+ (match_operand 1 "" "w"))
+ (match_operand 2 "aarch64_fp_const_vec" ""))
+ )]
+ ""
+ {
+ return "test_match";
+ }
+)
+
(define_insn "<optab><fcvt_target><VHSDF:mode>2"
[(set (match_operand:VHSDF 0 "register_operand" "=w")
(FLOATUORS:VHSDF
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 83453d03095..f836246e184 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -18327,6 +18327,12 @@ aarch64_fpconst_pow_of_2 (rtx x)
return exact_log2 (real_to_integer (r));
}
+int
+aarch64_fp_const_vec (rtx x)
+{
+ return GET_CODE (x) == CONST_VECTOR;
+}
+
/* If X is a vector of equal CONST_DOUBLE values and that value is
Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 10100ca830a..8fece3811b9 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -101,6 +101,9 @@
(define_predicate "aarch64_fp_vec_pow2"
(match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
+(define_predicate "aarch64_fp_const_vec"
+ (match_test "aarch64_fp_const_vec (op)"))
+
(define_predicate "aarch64_sve_cnt_immediate"
(and (match_code "const_poly_int")
(match_test "aarch64_sve_cnt_immediate_p (op)")))
--
2.17.1
void
bar (float *a, int *b)
{
int i;
for (i = 0; i < 1024; i++)
a[i] = (((float)b[i])/ 4.0f);
}
void
foo (float *a, int *b)
{
int i;
for (i = 0; i < 1024; i++)
b[i] = a[i] * 4.0f;
}
;; Function bar (bar, funcdef_no=0, decl_uid=3409, cgraph_uid=1, symbol_order=0)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 6 ( 1.2)
bar
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u} r97={1d,1u,1e}
r98={1d,1u} r99={1d,1u}
;; total ref usage 60{31d,28u,1e} in 11{11 regular + 0 call} insns.
;; Reaching defs:
;; sparse invalidated
;; dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 13, 14, 15, 16, 17,
18, 19, 22
;; reg->defs[] map: 0[0,0] 1[1,1] 2[2,2] 3[3,3] 4[4,4] 5[5,5] 6[6,6] 7[7,7]
8[8,8] 29[9,9] 30[10,10] 31[11,11] 32[12,12] 33[13,13] 34[14,14] 35[15,15]
36[16,16] 37[17,17] 38[18,18] 39[19,19] 64[20,20] 65[21,21] 66[22,22] 91[23,24]
94[25,25] 95[26,26] 96[27,27] 97[28,28] 98[29,29] 99[30,30]
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(0){ }d1(1){ }d2(2){ }d3(3){ }d4(4){ }d5(5){
}d6(6){ }d7(7){ }d8(8){ }d9(29){ }d10(30){ }d11(31){ }d12(32){ }d13(33){
}d14(34){ }d15(35){ }d16(36){ }d17(37){ }d18(38){ }d19(39){ }d20(64){ }d21(65){
}}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live kill
;; rd in (0)
;; rd gen (22)
0[0],1[1],2[2],3[3],4[4],5[5],6[6],7[7],8[8],29[9],30[10],31[11],32[12],33[13],34[14],35[15],36[16],37[17],38[18],39[19],64[20],65[21]
;; rd kill (22)
0[0],1[1],2[2],3[3],4[4],5[5],6[6],7[7],8[8],29[9],30[10],31[11],32[12],33[13],34[14],35[15],36[16],37[17],38[18],39[19],64[20],65[21]
;; UD chains for artificial uses at top
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; rd out (6) 0[0],1[1],29[9],31[11],64[20],65[21]
;; UD chains for artificial uses at bottom
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ d9(bb 0 insn -1) }u1(31){ d11(bb 0 insn -1)
}u2(64){ d20(bb 0 insn -1) }u3(65){ d21(bb 0 insn -1) }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 99
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 99
;; live kill
;; rd in (6) 0[0],1[1],29[9],31[11],64[20],65[21]
;; rd gen (4) 91[24],94[25],95[26],99[30]
;; rd kill (5) 91[23,24],94[25],95[26],99[30]
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; rd out (8) 29[9],31[11],64[20],65[21],91[24],94[25],95[26],99[30]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 2 3 )->[3]->( 3 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ d9(bb 0 insn -1) }u7(31){ d11(bb 0 insn -1)
}u8(64){ d20(bb 0 insn -1) }u9(65){ d21(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr def 66 [cc] 91 96 97 98
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live gen 66 [cc] 91 96 97 98
;; live kill
;; rd in (13)
29[9],31[11],64[20],65[21],66[22],91[23,24],94[25],95[26],96[27],97[28],98[29],99[30]
;; rd gen (5) 66[22],91[23],96[27],97[28],98[29]
;; rd kill (6) 66[22],91[23,24],96[27],97[28],98[29]
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; rd out (8) 29[9],31[11],64[20],65[21],91[23],94[25],95[26],99[30]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 3 )->[4]->( 1 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ d9(bb 0 insn -1) }u23(31){ d11(bb 0 insn
-1) }u24(64){ d20(bb 0 insn -1) }u25(65){ d21(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
;; rd in (8) 29[9],31[11],64[20],65[21],91[23],94[25],95[26],99[30]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; rd out (4) 29[9],31[11],64[20],65[21]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 4 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u26(29){ d9(bb 0 insn -1) }u27(31){ d11(bb 0 insn
-1) }u28(64){ d20(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp]
;; lr use 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; rd in (4) 29[9],31[11],64[20],65[21]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
;; lr out
;; live out
;; rd out (0)
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
Finding needed instructions:
Adding insn 17 to worklist
Adding insn 13 to worklist
Finished finding needed instructions:
Processing use of (reg 91 [ ivtmp.13 ]) in insn 13:
Adding insn 5 to worklist
Adding insn 14 to worklist
Processing use of (reg 94 [ a ]) in insn 13:
Adding insn 2 to worklist
Processing use of (reg 98 [ vect__7.7 ]) in insn 13:
Adding insn 12 to worklist
Processing use of (reg 97 [ vect__5.6 ]) in insn 12:
Adding insn 10 to worklist
Processing use of (reg 99) in insn 12:
Adding insn 11 to worklist
Processing use of (reg 96 [ vect__4.5 ]) in insn 10:
Adding insn 9 to worklist
Processing use of (reg 91 [ ivtmp.13 ]) in insn 9:
Processing use of (reg 95 [ b ]) in insn 9:
Adding insn 3 to worklist
Processing use of (reg 1 x1) in insn 3:
Processing use of (reg 0 x0) in insn 2:
Processing use of (reg 91 [ ivtmp.13 ]) in insn 14:
Processing use of (reg 66 cc) in insn 17:
Adding insn 16 to worklist
Processing use of (reg 91 [ ivtmp.13 ]) in insn 16:
starting the processing of deferred insns
ending the processing of deferred insns
bar
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u} r97={1d,1u,1e}
r98={1d,1u} r99={1d,1u}
;; total ref usage 60{31d,28u,1e} in 11{11 regular + 0 call} insns.
(note 6 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 6 3 2 (set (reg/v/f:DI 94 [ a ])
(reg:DI 0 x0 [ a ])) "bar.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 0 x0 [ a ])
(nil)))
(insn 3 2 4 2 (set (reg/v/f:DI 95 [ b ])
(reg:DI 1 x1 [ b ])) "bar.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 1 x1 [ b ])
(nil)))
(note 4 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 4 11 2 (set (reg:DI 91 [ ivtmp.13 ])
(const_int 0 [0])) "bar.c":3:1 47 {*movdi_aarch64}
(nil))
(insn 11 5 15 2 (set (reg:V4SF 99)
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
])) "bar.c":6:26 1149 {*aarch64_simd_movv4sf}
(nil))
(code_label 15 11 8 3 2 (nil) [1 uses])
(note 8 15 9 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 9 8 10 3 (set (reg:V4SI 96 [ vect__4.5 ])
(mem:V4SI (plus:DI (reg/v/f:DI 95 [ b ])
(reg:DI 91 [ ivtmp.13 ])) [1 MEM[base: b_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])) "bar.c":6:22 1146 {*aarch64_simd_movv4si}
(nil))
(insn 10 9 12 3 (set (reg:V4SF 97 [ vect__5.6 ])
(float:V4SF (reg:V4SI 96 [ vect__4.5 ]))) "bar.c":6:14 2070
{floatv4siv4sf2}
(expr_list:REG_DEAD (reg:V4SI 96 [ vect__4.5 ])
(nil)))
(insn 12 10 13 3 (set (reg:V4SF 98 [ vect__7.7 ])
(mult:V4SF (reg:V4SF 97 [ vect__5.6 ])
(reg:V4SF 99))) "bar.c":6:26 1901 {mulv4sf3}
(expr_list:REG_DEAD (reg:V4SF 97 [ vect__5.6 ])
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 97 [ vect__5.6 ])
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
]))
(nil))))
(insn 13 12 14 3 (set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ a ])
(reg:DI 91 [ ivtmp.13 ])) [2 MEM[base: a_12(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SF 98 [ vect__7.7 ])) "bar.c":6:10 1149 {*aarch64_simd_movv4sf}
(expr_list:REG_DEAD (reg:V4SF 98 [ vect__7.7 ])
(nil)))
(insn 14 13 16 3 (set (reg:DI 91 [ ivtmp.13 ])
(plus:DI (reg:DI 91 [ ivtmp.13 ])
(const_int 16 [0x10]))) 112 {*adddi3_aarch64}
(nil))
(insn 16 14 17 3 (set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ ivtmp.13 ])
(const_int 4096 [0x1000]))) 448 {cmpdi}
(nil))
(jump_insn 17 16 18 3 (set (pc)
(if_then_else (ne (reg:CC 66 cc)
(const_int 0 [0]))
(label_ref:DI 15)
(pc))) 9 {condjump}
(expr_list:REG_DEAD (reg:CC 66 cc)
(int_list:REG_BR_PROB 1030792158 (nil)))
-> 15)
(note 18 17 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; Function bar (bar, funcdef_no=0, decl_uid=3409, cgraph_uid=1, symbol_order=0)
Pass statistics of "combine": ----------------
scanning new insn with uid = 33.
rescanning insn with uid = 2.
scanning new insn with uid = 34.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 5 ( 1)
bar
Dataflow summary:
def_info->table_size = 31, use_info->table_size = 29
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u} r97={1d,1u,1e}
r98={1d,1u} r99={1d,1u} r100={1d,1u} r101={1d,1u}
;; total ref usage 64{33d,30u,1e} in 13{13 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(0){ }d1(1){ }d2(2){ }d3(3){ }d4(4){ }d5(5){
}d6(6){ }d7(7){ }d8(8){ }d9(29){ }d10(30){ }d11(31){ }d12(32){ }d13(33){
}d14(34){ }d15(35){ }d16(36){ }d17(37){ }d18(38){ }d19(39){ }d20(64){ }d21(65){
}}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live kill
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ }u1(31){ }u2(64){ }u3(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 99 100 101
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 99
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
( 2 3 )->[3]->( 3 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ }u7(31){ }u8(64){ }u9(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr def 66 [cc] 91 96 97 98
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live gen 66 [cc] 91 96 97 98
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
( 3 )->[4]->( 1 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ }u23(31){ }u24(64){ }u25(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 4 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u26(29){ }u27(31){ }u28(64){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp]
;; lr use 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 17 to worklist
Adding insn 13 to worklist
Finished finding needed instructions:
processing block 4 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
processing block 3 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
Adding insn 16 to worklist
Adding insn 14 to worklist
Adding insn 12 to worklist
Adding insn 10 to worklist
Adding insn 9 to worklist
processing block 2 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
Adding insn 11 to worklist
Adding insn 5 to worklist
Adding insn 3 to worklist
Adding insn 34 to worklist
Adding insn 2 to worklist
Adding insn 33 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 6 ( 1.2)
insn_cost 4 for 33: r100:DI=x0:DI
REG_DEAD x0:DI
insn_cost 4 for 2: r94:DI=r100:DI
REG_DEAD r100:DI
insn_cost 4 for 34: r101:DI=x1:DI
REG_DEAD x1:DI
insn_cost 4 for 3: r95:DI=r101:DI
REG_DEAD r101:DI
insn_cost 4 for 5: r91:DI=0
insn_cost 4 for 11: r99:V4SF=const_vector
insn_cost 8 for 9: r96:V4SI=[r95:DI+r91:DI]
insn_cost 8 for 10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
insn_cost 8 for 12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
insn_cost 4 for 13: [r94:DI+r91:DI]=r98:V4SF
REG_DEAD r98:V4SF
insn_cost 4 for 14: r91:DI=r91:DI+0x10
insn_cost 4 for 16: cc:CC=cmp(r91:DI,0x1000)
insn_cost 0 for 17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Trying 9 -> 10:
9: r96:V4SI=[r95:DI+r91:DI]
10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
Failed to match this instruction:
(set (reg:V4SF 97 [ D.3423 ])
(float:V4SF (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: b_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])))
Trying 10 -> 12:
10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
Failed to match this instruction:
(set (reg:V4SF 98 [ D.3424 ])
(mult:V4SF (float:V4SF (reg:V4SI 96 [ D.3422 ]))
(reg:V4SF 99)))
Trying 9, 10 -> 12:
9: r96:V4SI=[r95:DI+r91:DI]
10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
Failed to match this instruction:
(set (reg:V4SF 98 [ D.3424 ])
(mult:V4SF (float:V4SF (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: b_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32]))
(reg:V4SF 99)))
Failed to match this instruction:
(set (reg:V4SF 97 [ D.3423 ])
(float:V4SF (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: b_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])))
Trying 12 -> 13:
12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
13: [r94:DI+r91:DI]=r98:V4SF
REG_DEAD r98:V4SF
Failed to match this instruction:
(set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: a_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(mult:V4SF (reg:V4SF 97 [ D.3423 ])
(reg:V4SF 99)))
Trying 10, 12 -> 13:
10: r97:V4SF=float(r96:V4SI)
REG_DEAD r96:V4SI
12: r98:V4SF=r97:V4SF*r99:V4SF
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
13: [r94:DI+r91:DI]=r98:V4SF
REG_DEAD r98:V4SF
Failed to match this instruction:
(set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: a_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(mult:V4SF (float:V4SF (reg:V4SI 96 [ D.3422 ]))
(reg:V4SF 99)))
Successfully matched this instruction:
(set (reg:V4SF 98 [ D.3424 ])
(float:V4SF (reg:V4SI 96 [ D.3422 ])))
Failed to match this instruction:
(set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: a_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(mult:V4SF (reg:V4SF 98 [ D.3424 ])
(reg:V4SF 99)))
Trying 12 -> 13:
12: r98:V4SF=r97:V4SF*const_vector
REG_DEAD r97:V4SF
REG_EQUAL r97:V4SF*const_vector
13: [r94:DI+r91:DI]=r98:V4SF
REG_DEAD r98:V4SF
Failed to match this instruction:
(set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: a_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(mult:V4SF (reg:V4SF 97 [ D.3423 ])
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
])))
Trying 14 -> 16:
14: r91:DI=r91:DI+0x10
16: cc:CC=cmp(r91:DI,0x1000)
Failed to match this instruction:
(parallel [
(set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0])))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Failed to match this instruction:
(parallel [
(set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0])))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Trying 16 -> 17:
16: cc:CC=cmp(r91:DI,0x1000)
17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Failed to match this instruction:
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4096 [0x1000]))
(label_ref:DI 15)
(pc)))
Trying 14, 16 -> 17:
14: r91:DI=r91:DI+0x10
16: cc:CC=cmp(r91:DI,0x1000)
17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0]))
(label_ref:DI 15)
(pc)))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0]))
(label_ref:DI 15)
(pc)))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Pass statistics of "combine": ----------------
starting the processing of deferred insns
ending the processing of deferred insns
bar
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u} r97={1d,1u,1e}
r98={1d,1u} r99={1d,1u} r100={1d,1u} r101={1d,1u}
;; total ref usage 64{33d,30u,1e} in 13{13 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 10737418 (estimated locally), maybe hot
;; prev block 0, next block 3, flags: (RTL)
;; pred: ENTRY [always] count:10737418 (estimated locally) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ }u1(31){ }u2(64){ }u3(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 99 100 101
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 99 100 101
;; live kill
(note 6 0 33 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 33 6 2 2 (set (reg:DI 100)
(reg:DI 0 x0 [ aD.3407 ])) "bar.c":3:1 -1
(expr_list:REG_DEAD (reg:DI 0 x0 [ aD.3407 ])
(nil)))
(insn 2 33 34 2 (set (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 100)) "bar.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 100)
(nil)))
(insn 34 2 3 2 (set (reg:DI 101)
(reg:DI 1 x1 [ bD.3408 ])) "bar.c":3:1 -1
(expr_list:REG_DEAD (reg:DI 1 x1 [ bD.3408 ])
(nil)))
(insn 3 34 4 2 (set (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 101)) "bar.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 101)
(nil)))
(note 4 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 4 11 2 (set (reg:DI 91 [ D.3430 ])
(const_int 0 [0])) "bar.c":3:1 47 {*movdi_aarch64}
(nil))
(insn 11 5 15 2 (set (reg:V4SF 99)
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
])) "bar.c":6:26 1149 {*aarch64_simd_movv4sf}
(nil))
;; succ: 3 [always] count:10737418 (estimated locally) (FALLTHRU)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; basic block 3, loop depth 0, count 268435451 (estimated locally), maybe hot
;; prev block 2, next block 4, flags: (RTL)
;; pred: 2 [always] count:10737418 (estimated locally) (FALLTHRU)
;; 3 [96.0% (adjusted)] count:257698033 (estimated locally)
(DFS_BACK)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ }u7(31){ }u8(64){ }u9(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; lr def 66 [cc] 91 96 97 98
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live gen 66 [cc] 91 96 97 98
;; live kill
(code_label 15 11 8 3 2 (nil) [1 uses])
(note 8 15 9 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 9 8 10 3 (set (reg:V4SI 96 [ D.3422 ])
(mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: b_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])) "bar.c":6:22 1146 {*aarch64_simd_movv4si}
(nil))
(insn 10 9 12 3 (set (reg:V4SF 97 [ D.3423 ])
(float:V4SF (reg:V4SI 96 [ D.3422 ]))) "bar.c":6:14 2070
{floatv4siv4sf2}
(expr_list:REG_DEAD (reg:V4SI 96 [ D.3422 ])
(nil)))
(insn 12 10 13 3 (set (reg:V4SF 98 [ D.3424 ])
(mult:V4SF (reg:V4SF 97 [ D.3423 ])
(reg:V4SF 99))) "bar.c":6:26 1901 {mulv4sf3}
(expr_list:REG_DEAD (reg:V4SF 97 [ D.3423 ])
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 97 [ D.3423 ])
(const_vector:V4SF [
(const_double:SF 2.5e-1 [0x0.8p-1]) repeated x4
]))
(nil))))
(insn 13 12 14 3 (set (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: a_12(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SF 98 [ D.3424 ])) "bar.c":6:10 1149 {*aarch64_simd_movv4sf}
(expr_list:REG_DEAD (reg:V4SF 98 [ D.3424 ])
(nil)))
(insn 14 13 16 3 (set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10]))) 112 {*adddi3_aarch64}
(nil))
(insn 16 14 17 3 (set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4096 [0x1000]))) 448 {cmpdi}
(nil))
(jump_insn 17 16 18 3 (set (pc)
(if_then_else (ne (reg:CC 66 cc)
(const_int 0 [0]))
(label_ref:DI 15)
(pc))) 9 {condjump}
(expr_list:REG_DEAD (reg:CC 66 cc)
(int_list:REG_BR_PROB 1030792158 (nil)))
-> 15)
;; succ: 3 [96.0% (adjusted)] count:257698033 (estimated locally)
(DFS_BACK)
;; 4 [4.0% (adjusted)] count:10737418 (estimated locally)
(FALLTHRU,LOOP_EXIT)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 99
;; basic block 4, loop depth 0, count 10737418 (estimated locally), maybe hot
;; prev block 3, next block 1, flags: (RTL)
;; pred: 3 [4.0% (adjusted)] count:10737418 (estimated locally)
(FALLTHRU,LOOP_EXIT)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ }u23(31){ }u24(64){ }u25(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
(note 18 17 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; succ: EXIT [always] count:10737418 (estimated locally) (FALLTHRU)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; Combiner totals: 9 attempts, 9 substitutions (2 requiring new space),
;; 0 successes.
;; Function foo (foo, funcdef_no=0, decl_uid=3409, cgraph_uid=1, symbol_order=0)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 6 ( 1.2)
foo
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u,1e} r97={1d,1u}
r98={1d,1u} r99={1d,1u}
;; total ref usage 60{31d,28u,1e} in 11{11 regular + 0 call} insns.
;; Reaching defs:
;; sparse invalidated
;; dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 13, 14, 15, 16, 17,
18, 19, 22
;; reg->defs[] map: 0[0,0] 1[1,1] 2[2,2] 3[3,3] 4[4,4] 5[5,5] 6[6,6] 7[7,7]
8[8,8] 29[9,9] 30[10,10] 31[11,11] 32[12,12] 33[13,13] 34[14,14] 35[15,15]
36[16,16] 37[17,17] 38[18,18] 39[19,19] 64[20,20] 65[21,21] 66[22,22] 91[23,24]
94[25,25] 95[26,26] 96[27,27] 97[28,28] 98[29,29] 99[30,30]
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(0){ }d1(1){ }d2(2){ }d3(3){ }d4(4){ }d5(5){
}d6(6){ }d7(7){ }d8(8){ }d9(29){ }d10(30){ }d11(31){ }d12(32){ }d13(33){
}d14(34){ }d15(35){ }d16(36){ }d17(37){ }d18(38){ }d19(39){ }d20(64){ }d21(65){
}}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live kill
;; rd in (0)
;; rd gen (22)
0[0],1[1],2[2],3[3],4[4],5[5],6[6],7[7],8[8],29[9],30[10],31[11],32[12],33[13],34[14],35[15],36[16],37[17],38[18],39[19],64[20],65[21]
;; rd kill (22)
0[0],1[1],2[2],3[3],4[4],5[5],6[6],7[7],8[8],29[9],30[10],31[11],32[12],33[13],34[14],35[15],36[16],37[17],38[18],39[19],64[20],65[21]
;; UD chains for artificial uses at top
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; rd out (6) 0[0],1[1],29[9],31[11],64[20],65[21]
;; UD chains for artificial uses at bottom
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ d9(bb 0 insn -1) }u1(31){ d11(bb 0 insn -1)
}u2(64){ d20(bb 0 insn -1) }u3(65){ d21(bb 0 insn -1) }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 98
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 98
;; live kill
;; rd in (6) 0[0],1[1],29[9],31[11],64[20],65[21]
;; rd gen (4) 91[24],94[25],95[26],98[29]
;; rd kill (5) 91[23,24],94[25],95[26],98[29]
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; rd out (8) 29[9],31[11],64[20],65[21],91[24],94[25],95[26],98[29]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 2 3 )->[3]->( 3 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ d9(bb 0 insn -1) }u7(31){ d11(bb 0 insn -1)
}u8(64){ d20(bb 0 insn -1) }u9(65){ d21(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr def 66 [cc] 91 96 97 99
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live gen 66 [cc] 91 96 97 99
;; live kill
;; rd in (13)
29[9],31[11],64[20],65[21],66[22],91[23,24],94[25],95[26],96[27],97[28],98[29],99[30]
;; rd gen (5) 66[22],91[23],96[27],97[28],99[30]
;; rd kill (6) 66[22],91[23,24],96[27],97[28],99[30]
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; rd out (8) 29[9],31[11],64[20],65[21],91[23],94[25],95[26],98[29]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 3 )->[4]->( 1 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ d9(bb 0 insn -1) }u23(31){ d11(bb 0 insn
-1) }u24(64){ d20(bb 0 insn -1) }u25(65){ d21(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
;; rd in (8) 29[9],31[11],64[20],65[21],91[23],94[25],95[26],98[29]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; rd out (4) 29[9],31[11],64[20],65[21]
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
;; reg 65 { d21(bb 0 insn -1) }
( 4 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u26(29){ d9(bb 0 insn -1) }u27(31){ d11(bb 0 insn
-1) }u28(64){ d20(bb 0 insn -1) }}
;; lr in 29 [x29] 31 [sp] 64 [sfp]
;; lr use 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; rd in (4) 29[9],31[11],64[20],65[21]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
;; lr out
;; live out
;; rd out (0)
;; UD chains for artificial uses at bottom
;; reg 29 { d9(bb 0 insn -1) }
;; reg 31 { d11(bb 0 insn -1) }
;; reg 64 { d20(bb 0 insn -1) }
Finding needed instructions:
Adding insn 17 to worklist
Adding insn 13 to worklist
Finished finding needed instructions:
Processing use of (reg 91 [ ivtmp.13 ]) in insn 13:
Adding insn 5 to worklist
Adding insn 14 to worklist
Processing use of (reg 95 [ b ]) in insn 13:
Adding insn 3 to worklist
Processing use of (reg 99 [ vect__7.7 ]) in insn 13:
Adding insn 12 to worklist
Processing use of (reg 97 [ vect__5.6 ]) in insn 12:
Adding insn 11 to worklist
Processing use of (reg 96 [ vect__4.5 ]) in insn 11:
Adding insn 9 to worklist
Processing use of (reg 98) in insn 11:
Adding insn 10 to worklist
Processing use of (reg 91 [ ivtmp.13 ]) in insn 9:
Processing use of (reg 94 [ a ]) in insn 9:
Adding insn 2 to worklist
Processing use of (reg 0 x0) in insn 2:
Processing use of (reg 1 x1) in insn 3:
Processing use of (reg 91 [ ivtmp.13 ]) in insn 14:
Processing use of (reg 66 cc) in insn 17:
Adding insn 16 to worklist
Processing use of (reg 91 [ ivtmp.13 ]) in insn 16:
starting the processing of deferred insns
ending the processing of deferred insns
foo
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u,1e} r97={1d,1u}
r98={1d,1u} r99={1d,1u}
;; total ref usage 60{31d,28u,1e} in 11{11 regular + 0 call} insns.
(note 6 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 6 3 2 (set (reg/v/f:DI 94 [ a ])
(reg:DI 0 x0 [ a ])) "foo.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 0 x0 [ a ])
(nil)))
(insn 3 2 4 2 (set (reg/v/f:DI 95 [ b ])
(reg:DI 1 x1 [ b ])) "foo.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 1 x1 [ b ])
(nil)))
(note 4 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 4 10 2 (set (reg:DI 91 [ ivtmp.13 ])
(const_int 0 [0])) "foo.c":3:1 47 {*movdi_aarch64}
(nil))
(insn 10 5 15 2 (set (reg:V4SF 98)
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
])) "foo.c":6:17 1149 {*aarch64_simd_movv4sf}
(nil))
(code_label 15 10 8 3 2 (nil) [1 uses])
(note 8 15 9 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 9 8 11 3 (set (reg:V4SF 96 [ vect__4.5 ])
(mem:V4SF (plus:DI (reg/v/f:DI 94 [ a ])
(reg:DI 91 [ ivtmp.13 ])) [1 MEM[base: a_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])) "foo.c":6:13 1149 {*aarch64_simd_movv4sf}
(nil))
(insn 11 9 12 3 (set (reg:V4SF 97 [ vect__5.6 ])
(mult:V4SF (reg:V4SF 96 [ vect__4.5 ])
(reg:V4SF 98))) "foo.c":6:17 1901 {mulv4sf3}
(expr_list:REG_DEAD (reg:V4SF 96 [ vect__4.5 ])
(expr_list:REG_EQUAL (mult:V4SF (reg:V4SF 96 [ vect__4.5 ])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
(nil))))
(insn 12 11 13 3 (set (reg:V4SI 99 [ vect__7.7 ])
(fix:V4SI (unspec:V4SI [
(reg:V4SF 97 [ vect__5.6 ])
] UNSPEC_FRINTZ))) "foo.c":6:10 2023 {lbtruncv4sfv4si2}
(expr_list:REG_DEAD (reg:V4SF 97 [ vect__5.6 ])
(nil)))
(insn 13 12 14 3 (set (mem:V4SI (plus:DI (reg/v/f:DI 95 [ b ])
(reg:DI 91 [ ivtmp.13 ])) [2 MEM[base: b_12(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SI 99 [ vect__7.7 ])) "foo.c":6:10 1146 {*aarch64_simd_movv4si}
(expr_list:REG_DEAD (reg:V4SI 99 [ vect__7.7 ])
(nil)))
(insn 14 13 16 3 (set (reg:DI 91 [ ivtmp.13 ])
(plus:DI (reg:DI 91 [ ivtmp.13 ])
(const_int 16 [0x10]))) 112 {*adddi3_aarch64}
(nil))
(insn 16 14 17 3 (set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ ivtmp.13 ])
(const_int 4096 [0x1000]))) 448 {cmpdi}
(nil))
(jump_insn 17 16 18 3 (set (pc)
(if_then_else (ne (reg:CC 66 cc)
(const_int 0 [0]))
(label_ref:DI 15)
(pc))) 9 {condjump}
(expr_list:REG_DEAD (reg:CC 66 cc)
(int_list:REG_BR_PROB 1030792158 (nil)))
-> 15)
(note 18 17 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; Function foo (foo, funcdef_no=0, decl_uid=3409, cgraph_uid=1, symbol_order=0)
Pass statistics of "combine": ----------------
scanning new insn with uid = 33.
rescanning insn with uid = 2.
scanning new insn with uid = 34.
rescanning insn with uid = 3.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 5 ( 1)
foo
Dataflow summary:
def_info->table_size = 31, use_info->table_size = 29
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u,1e} r97={1d,1u}
r98={1d,1u} r99={1d,1u} r100={1d,1u} r101={1d,1u}
;; total ref usage 64{33d,30u,1e} in 13{13 regular + 0 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d0(0){ }d1(1){ }d2(2){ }d3(3){ }d4(4){ }d5(5){
}d6(6){ }d7(7){ }d8(8){ }d9(29){ }d10(30){ }d11(31){ }d12(32){ }d13(33){
}d14(34){ }d15(35){ }d16(36){ }d17(37){ }d18(38){ }d19(39){ }d20(64){ }d21(65){
}}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live in
;; live gen 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7 [x7] 8 [x8]
29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37 [v5] 38
[v6] 39 [v7] 64 [sfp] 65 [ap]
;; live kill
;; lr out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 0 )->[2]->( 3 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ }u1(31){ }u2(64){ }u3(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 98 100 101
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 98
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
( 2 3 )->[3]->( 3 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ }u7(31){ }u8(64){ }u9(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr def 66 [cc] 91 96 97 99
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live gen 66 [cc] 91 96 97 99
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
( 3 )->[4]->( 1 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ }u23(31){ }u24(64){ }u25(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
( 4 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u26(29){ }u27(31){ }u28(64){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp]
;; lr use 29 [x29] 31 [sp] 64 [sfp]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
Finding needed instructions:
Adding insn 17 to worklist
Adding insn 13 to worklist
Finished finding needed instructions:
processing block 4 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
processing block 3 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
Adding insn 16 to worklist
Adding insn 14 to worklist
Adding insn 12 to worklist
Adding insn 11 to worklist
Adding insn 9 to worklist
processing block 2 lr out = 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
Adding insn 10 to worklist
Adding insn 5 to worklist
Adding insn 3 to worklist
Adding insn 34 to worklist
Adding insn 2 to worklist
Adding insn 33 to worklist
df_worklist_dataflow_doublequeue: n_basic_blocks 5 n_edges 5 count 6 ( 1.2)
insn_cost 4 for 33: r100:DI=x0:DI
REG_DEAD x0:DI
insn_cost 4 for 2: r94:DI=r100:DI
REG_DEAD r100:DI
insn_cost 4 for 34: r101:DI=x1:DI
REG_DEAD x1:DI
insn_cost 4 for 3: r95:DI=r101:DI
REG_DEAD r101:DI
insn_cost 4 for 5: r91:DI=0
insn_cost 4 for 10: r98:V4SF=const_vector
insn_cost 8 for 9: r96:V4SF=[r94:DI+r91:DI]
insn_cost 8 for 11: r97:V4SF=r96:V4SF*r98:V4SF
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
insn_cost 8 for 12: r99:V4SI=fix(unspec[r97:V4SF] 25)
REG_DEAD r97:V4SF
insn_cost 4 for 13: [r95:DI+r91:DI]=r99:V4SI
REG_DEAD r99:V4SI
insn_cost 4 for 14: r91:DI=r91:DI+0x10
insn_cost 4 for 16: cc:CC=cmp(r91:DI,0x1000)
insn_cost 0 for 17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Trying 9 -> 11:
9: r96:V4SF=[r94:DI+r91:DI]
11: r97:V4SF=r96:V4SF*r98:V4SF
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
Failed to match this instruction:
(set (reg:V4SF 97 [ D.3423 ])
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SF 98)))
Trying 11 -> 12:
11: r97:V4SF=r96:V4SF*r98:V4SF
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
12: r99:V4SI=fix(unspec[r97:V4SF] 25)
REG_DEAD r97:V4SF
Failed to match this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (reg:V4SF 96 [ D.3422 ])
(reg:V4SF 98))
] UNSPEC_FRINTZ)))
Trying 9, 11 -> 12:
9: r96:V4SF=[r94:DI+r91:DI]
11: r97:V4SF=r96:V4SF*r98:V4SF
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
12: r99:V4SI=fix(unspec[r97:V4SF] 25)
REG_DEAD r97:V4SF
Failed to match this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D),
index: ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SF 98))
] UNSPEC_FRINTZ)))
Failed to match this instruction:
(set (reg:V4SI 97 [ D.3423 ])
(unspec:V4SI [
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SF 98))
] UNSPEC_FRINTZ))
Trying 11 -> 12:
11: r97:V4SF=r96:V4SF*const_vector
REG_DEAD r96:V4SF
REG_EQUAL r96:V4SF*const_vector
12: r99:V4SI=fix(unspec[r97:V4SF] 25)
REG_DEAD r97:V4SF
Successfully matched this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (reg:V4SF 96 [ D.3422 ])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ)))
allowing combination of insns 11 and 12
original costs 8 + 8 = 16
replacement cost 8
deferring deletion of insn with uid = 11.
modifying insn i3 12: r99:V4SI=fix(unspec[r96:V4SF*const_vector] 25)
REG_DEAD r96:V4SF
deferring rescan insn with uid = 12.
Trying 9 -> 12:
9: r96:V4SF=[r94:DI+r91:DI]
12: r99:V4SI=fix(unspec[r96:V4SF*const_vector] 25)
REG_DEAD r96:V4SF
Failed to match this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D),
index: ivtmp.13_21, offset: 0B]+0 S16 A32])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ)))
Trying 12 -> 13:
12: r99:V4SI=fix(unspec[r96:V4SF*const_vector] 25)
REG_DEAD r96:V4SF
13: [r95:DI+r91:DI]=r99:V4SI
REG_DEAD r99:V4SI
Failed to match this instruction:
(set (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: b_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (reg:V4SF 96 [ D.3422 ])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ)))
Trying 9, 12 -> 13:
9: r96:V4SF=[r94:DI+r91:DI]
12: r99:V4SI=fix(unspec[r96:V4SF*const_vector] 25)
REG_DEAD r96:V4SF
13: [r95:DI+r91:DI]=r99:V4SI
REG_DEAD r99:V4SI
Failed to match this instruction:
(set (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: b_12(D), index: ivtmp.13_21,
offset: 0B]+0 S16 A32])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D),
index: ivtmp.13_21, offset: 0B]+0 S16 A32])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ)))
Failed to match this instruction:
(set (reg:V4SI 99 [ D.3424 ])
(unspec:V4SI [
(mult:V4SF (mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ))
Trying 14 -> 16:
14: r91:DI=r91:DI+0x10
16: cc:CC=cmp(r91:DI,0x1000)
Failed to match this instruction:
(parallel [
(set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0])))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Failed to match this instruction:
(parallel [
(set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0])))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Trying 16 -> 17:
16: cc:CC=cmp(r91:DI,0x1000)
17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Failed to match this instruction:
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4096 [0x1000]))
(label_ref:DI 15)
(pc)))
Trying 14, 16 -> 17:
14: r91:DI=r91:DI+0x10
16: cc:CC=cmp(r91:DI,0x1000)
17: pc={(cc:CC!=0)?L15:pc}
REG_DEAD cc:CC
REG_BR_PROB 1030792158
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0]))
(label_ref:DI 15)
(pc)))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Failed to match this instruction:
(parallel [
(set (pc)
(if_then_else (ne (reg:DI 91 [ D.3430 ])
(const_int 4080 [0xff0]))
(label_ref:DI 15)
(pc)))
(set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10])))
])
Pass statistics of "combine": ----------------
insn-with-note combine: 1
starting the processing of deferred insns
rescanning insn with uid = 12.
ending the processing of deferred insns
foo
Dataflow summary:
;; invalidated by call 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6
[x6] 7 [x7] 8 [x8] 9 [x9] 10 [x10] 11 [x11] 12 [x12] 13 [x13] 14 [x14] 15 [x15]
16 [x16] 17 [x17] 18 [x18] 30 [x30] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4] 37
[v5] 38 [v6] 39 [v7] 48 [v16] 49 [v17] 50 [v18] 51 [v19] 52 [v20] 53 [v21] 54
[v22] 55 [v23] 56 [v24] 57 [v25] 58 [v26] 59 [v27] 60 [v28] 61 [v29] 62 [v30]
63 [v31] 66 [cc] 67 [vg] 68 [p0] 69 [p1] 70 [p2] 71 [p3] 72 [p4] 73 [p5] 74
[p6] 75 [p7] 76 [p8] 77 [p9] 78 [p10] 79 [p11] 80 [p12] 81 [p13] 82 [p14] 83
[p15]
;; hardware regs used 31 [sp] 64 [sfp] 65 [ap]
;; regular block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; eh block artificial uses 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; entry block defs 0 [x0] 1 [x1] 2 [x2] 3 [x3] 4 [x4] 5 [x5] 6 [x6] 7
[x7] 8 [x8] 29 [x29] 30 [x30] 31 [sp] 32 [v0] 33 [v1] 34 [v2] 35 [v3] 36 [v4]
37 [v5] 38 [v6] 39 [v7] 64 [sfp] 65 [ap]
;; exit block uses 29 [x29] 31 [sp] 64 [sfp]
;; regs ever live 0 [x0] 1 [x1] 66 [cc]
;; ref usage r0={1d,1u} r1={1d,1u} r2={1d} r3={1d} r4={1d} r5={1d} r6={1d}
r7={1d} r8={1d} r29={1d,4u} r30={1d} r31={1d,4u} r32={1d} r33={1d} r34={1d}
r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r64={1d,4u} r65={1d,3u}
r66={1d,1u} r91={2d,4u} r94={1d,1u} r95={1d,1u} r96={1d,1u} r98={1d}
r99={1d,1u} r100={1d,1u} r101={1d,1u}
;; total ref usage 60{32d,28u,0e} in 12{12 regular + 0 call} insns.
;; basic block 2, loop depth 0, count 10737418 (estimated locally), maybe hot
;; prev block 0, next block 3, flags: (RTL)
;; pred: ENTRY [always] count:10737418 (estimated locally) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(29){ }u1(31){ }u2(64){ }u3(65){ }}
;; lr in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def 91 94 95 98 100 101
;; live in 0 [x0] 1 [x1] 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen 91 94 95 98 100 101
;; live kill
(note 6 0 33 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 33 6 2 2 (set (reg:DI 100)
(reg:DI 0 x0 [ aD.3407 ])) "foo.c":3:1 -1
(expr_list:REG_DEAD (reg:DI 0 x0 [ aD.3407 ])
(nil)))
(insn 2 33 34 2 (set (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 100)) "foo.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 100)
(nil)))
(insn 34 2 3 2 (set (reg:DI 101)
(reg:DI 1 x1 [ bD.3408 ])) "foo.c":3:1 -1
(expr_list:REG_DEAD (reg:DI 1 x1 [ bD.3408 ])
(nil)))
(insn 3 34 4 2 (set (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 101)) "foo.c":3:1 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 101)
(nil)))
(note 4 3 5 2 NOTE_INSN_FUNCTION_BEG)
(insn 5 4 10 2 (set (reg:DI 91 [ D.3430 ])
(const_int 0 [0])) "foo.c":3:1 47 {*movdi_aarch64}
(nil))
(insn 10 5 15 2 (set (reg:V4SF 98)
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
])) "foo.c":6:17 1149 {*aarch64_simd_movv4sf}
(nil))
;; succ: 3 [always] count:10737418 (estimated locally) (FALLTHRU)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; basic block 3, loop depth 0, count 268435451 (estimated locally), maybe hot
;; prev block 2, next block 4, flags: (RTL, MODIFIED)
;; pred: 2 [always] count:10737418 (estimated locally) (FALLTHRU)
;; 3 [96.0% (adjusted)] count:257698033 (estimated locally)
(DFS_BACK)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u6(29){ }u7(31){ }u8(64){ }u9(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; lr def 66 [cc] 91 96 97 99
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live gen 66 [cc] 91 96 97 99
;; live kill
(code_label 15 10 8 3 2 (nil) [1 uses])
(note 8 15 9 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 9 8 11 3 (set (reg:V4SF 96 [ D.3422 ])
(mem:V4SF (plus:DI (reg/v/f:DI 94 [ aD.3407 ])
(reg:DI 91 [ D.3430 ])) [1 MEM[base: a_11(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])) "foo.c":6:13 1149 {*aarch64_simd_movv4sf}
(nil))
(note 11 9 12 3 NOTE_INSN_DELETED)
(insn 12 11 13 3 (set (reg:V4SI 99 [ D.3424 ])
(fix:V4SI (unspec:V4SI [
(mult:V4SF (reg:V4SF 96 [ D.3422 ])
(const_vector:V4SF [
(const_double:SF 4.0e+0 [0x0.8p+3]) repeated x4
]))
] UNSPEC_FRINTZ))) "foo.c":6:10 2059
{*aarch64_fcvtv4sfv4si2_mult}
(expr_list:REG_DEAD (reg:V4SF 96 [ D.3422 ])
(nil)))
(insn 13 12 14 3 (set (mem:V4SI (plus:DI (reg/v/f:DI 95 [ bD.3408 ])
(reg:DI 91 [ D.3430 ])) [2 MEM[base: b_12(D), index:
ivtmp.13_21, offset: 0B]+0 S16 A32])
(reg:V4SI 99 [ D.3424 ])) "foo.c":6:10 1146 {*aarch64_simd_movv4si}
(expr_list:REG_DEAD (reg:V4SI 99 [ D.3424 ])
(nil)))
(insn 14 13 16 3 (set (reg:DI 91 [ D.3430 ])
(plus:DI (reg:DI 91 [ D.3430 ])
(const_int 16 [0x10]))) 112 {*adddi3_aarch64}
(nil))
(insn 16 14 17 3 (set (reg:CC 66 cc)
(compare:CC (reg:DI 91 [ D.3430 ])
(const_int 4096 [0x1000]))) 448 {cmpdi}
(nil))
(jump_insn 17 16 18 3 (set (pc)
(if_then_else (ne (reg:CC 66 cc)
(const_int 0 [0]))
(label_ref:DI 15)
(pc))) 9 {condjump}
(expr_list:REG_DEAD (reg:CC 66 cc)
(int_list:REG_BR_PROB 1030792158 (nil)))
-> 15)
;; succ: 3 [96.0% (adjusted)] count:257698033 (estimated locally)
(DFS_BACK)
;; 4 [4.0% (adjusted)] count:10737418 (estimated locally)
(FALLTHRU,LOOP_EXIT)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap] 91 94 95 98
;; basic block 4, loop depth 0, count 10737418 (estimated locally), maybe hot
;; prev block 3, next block 1, flags: (RTL)
;; pred: 3 [4.0% (adjusted)] count:10737418 (estimated locally)
(FALLTHRU,LOOP_EXIT)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u22(29){ }u23(31){ }u24(64){ }u25(65){ }}
;; lr in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr use 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; lr def
;; live in 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live gen
;; live kill
(note 18 17 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; succ: EXIT [always] count:10737418 (estimated locally) (FALLTHRU)
;; lr out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; live out 29 [x29] 31 [sp] 64 [sfp] 65 [ap]
;; Combiner totals: 10 attempts, 10 substitutions (2 requiring new space),
;; 1 successes.
