Hi Nathan,
Thanks for your advice. I retooled the addhi3 sequence to look like this:
(define_expand "addhi3"
[(set (match_operand:HI 0 "snap_mem_or_reg" "+a,m")
(plus:HI (match_operand:HI 1 "snap_mem_or_reg" "%0,0")
(match_operand:HI 2 "general_operand" "aim,aim")))]
""
""
)
(define_insn "addhi3_regtarget"
[(set (match_operand:HI 0 "register_operand" "+a")
(plus:HI (match_operand:HI 1 "register_operand" "%0")
(match_operand:HI 2 "general_operand" "aim")))]
""
{
output_asm_insn("//Start of addhi3_regtarget %0 = %1 + %2", operands);
snap_do_basic_math_op_hi(operands, MATH_OP_PLUS);
output_asm_insn("//End of addhi3_regtarget", operands);
return("");
}
)
(define_insn "addhi3_memtarget"
[(set (match_operand:HI 0 "memory_operand" "+m")
(plus:HI (match_operand:HI 1 "memory_operand" "%0")
(match_operand:HI 2 "general_operand" "aim")))]
""
{
output_asm_insn("//Start of addhi3_memtarget %0 = %1 + %2", operands);
snap_do_basic_math_op_hi(operands, MATH_OP_PLUS);
output_asm_insn("//End of addhi3_memtarget", operands);
return("");
}
)
I compile a simple program with this:
void addit()
{
int a, b, c;
a = -10;
b = 2;
c = a + b;
}
And the compiler fails out with the following message:
addit.c: In function 'addit':
addit.c:12:1: internal compiler error: in find_reloads, at reload.c:4085
}
^
0x8f5953 find_reloads(rtx_insn*, int, int, int, short*)
../../gcc-6.2.0/gcc/reload.c:4085
0x90327b calculate_needs_all_insns
../../gcc-6.2.0/gcc/reload1.c:1484
0x90327b reload(rtx_insn*, int)
../../gcc-6.2.0/gcc/reload1.c:995
0x7e8f11 do_reload
../../gcc-6.2.0/gcc/ira.c:5437
0x7e8f11 execute
../../gcc-6.2.0/gcc/ira.c:5609
It would seem that the constraints are somehow not right, but I am not familiar
with the particular way the compiler does this step. Any insights or pointers?
Thanks,
Steve S
On Tuesday, January 17, 2017 12:45 PM, Nathan Sidwell <[email protected]> wrote:
On 01/17/2017 12:19 PM, Steve Silva via gcc wrote:
> Hi All,
>
>
> I am porting gcc for an internal processor and I am having some issues with
> math instructions. Our processor uses two operands for math instructions
> which are usually of the form OP0 = OP0 + OP1. The RTL pattern (for addm3)
> in gcc uses the form OP0 = OP1 + OP2. I understand that gcc supposedly
> supports the two operand flavor, but I have not been able to convince it to
> do that for me. I tried the following RTL pattern with no success:
> So I used the three operand form and fixed things up in the code:
That's nearly right.
Use register constraints with the 3 op pattern:
(define_insn "addhi3"
[(set (match_operand:HI 0 "register_operand" "+a")
(plus:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "aim")))]
The sh port may be instructive, IIRC it has a bunch of 2-op insns.
nathan
--
Nathan Sidwell
