On 01/17/2017 12:19 PM, Steve Silva via gcc wrote:
Hi All,
I am porting gcc for an internal processor and I am having some issues with
math instructions. Our processor uses two operands for math instructions which
are usually of the form OP0 = OP0 + OP1. The RTL pattern (for addm3) in gcc
uses the form OP0 = OP1 + OP2. I understand that gcc supposedly supports the
two operand flavor, but I have not been able to convince it to do that for me.
I tried the following RTL pattern with no success:
So I used the three operand form and fixed things up in the code:
That's nearly right.
Use register constraints with the 3 op pattern:
(define_insn "addhi3"
[(set (match_operand:HI 0 "register_operand" "+a")
(plus:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "aim")))]
The sh port may be instructive, IIRC it has a bunch of 2-op insns.
nathan
--
Nathan Sidwell
