Quoting Paulo Matos <pma...@broadcom.com>:
Hello,I am trying to model a predicate register mode that acts like a vector. We have a few predicate registers that have 8 bits in size but they are set accordingly to the mode of operation (not necessarily a comparison). Word size is 64.
Yes need some surgery to the mode generator machinery. I had the same problem with the mxp port, which you can still find in older ARC branches.
