On Sun, 6 Nov 2011, Joern Rennecke wrote:
> Quoting David Brown <david.br...@hesbynett.no>:
>
> > Take an example using a processor I know well, the AVR (it is an 8-bit
> > device, which is a little unusual for gcc). It has an instruction will
> > multiply two "1.7" signed 8-bit integers to get a single 1.15 signed
> > 16-bit integer - basically combining an 8-bit x 8-bit to 16-bit
> > multiply with a left shift. So to do a "signed short _Fract" multiply,
> > you have a single instruction and discard the least significant byte.
> >
> > Simulating the same operation in generic C would be something like :
> >
> > int8_t multShortFract(int8_t a, int8_t b) {
> > int16_t c = (int16_t) a * b;
> > return (c >> 7);
> > }
>
> If you can make up your mind if the result is 8 or 16 bit, generating the
> instruction should be standard fare for the combiner pass.
Looks like a pretty typical Q7 (or Q1.7) multiplication to me
unless I miss something... Would be a nice thing to have those
Q1.<N-1> formats as native GCC-extension types including
vectorized versions. No, not planning it.
And having intermediate calculations in a wider mode does not
constituate lack of making ones mind up. :)
Though I believe that cast of "a" is ineffective, IIUC.
brgds, H-P
