Hello,
I would like to implement a compiler fix for a SPARC-cpu variant
that does the following:
After each "fdivs" (SPARC single-float division) save the destination
FPU register to a stack memory location.
The sparc.md definition of fdivs is this one:
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_FPU"
"fdivs\t%1, %2, %0"
[(set_attr "type" "fpdivs")])
What is the best way to accomplish that exactly after
the "fdivs\t%1, %2, %0" a "st %0, [<memory>]" is issued? where
<memory> is a stack location that is allocated for each "divsf3"
insn?
Is something similar for other architectures?
It seems I cannot use the sparc_reorg pass hook because the
stackframe might be > 4096 and a new register has to be
allocated before for the store address... Is there
some hook before the reload pass that I could use?
-- Thanks Konrad
