Eric Botcazou wrote:
> So I'd suggest that Luís Vitório and/or Konrad do the required paperwork, and
> then start to post their patches on the gcc-patches@ list. I'll sponsor them
> for write access at that point.
>
Hello Eric Botcazou,
I want to once again ask for write credentials so that
I can submit patches for the sparc-leon architecture:
The first patch is for the 'gcc' repository while the
second patch is for the 'binutils' repository. They are both
related so I think it makes sense to send them together.
I dont have write access to binutils eather so, I thought you
might be able to apply them on both.
Some background: Leon supports the umac/smac instructions.
The Leon3-Ft and Leon4 also support the SMP compare-and-swap (casa)
v9-instruction. The appended 2 patches do:
1. 0001-sparc-leon-Use-Aleon-assembler-switch-for-mcpu-leon-.patch
Append "-Aleon" to the assembler
2. 0001-sparc-leon-add-leon-architecture-to-GAS.patch
Define new "leon" processor type in GAS + enable for "leon"
umac/smac and "casa".
It would help a lot if you could apply this for us once more.
-- Greetings Konrad
>From 2d799b053e78383a3029845aee858487225004e3 Mon Sep 17 00:00:00 2001
From: Konrad Eisele <kon...@gaisler.com>
Date: Fri, 21 Oct 2011 14:30:58 +0200
Subject: [PATCH 1/1] sparc leon: Use -Aleon assembler switch for -mcpu=leon arch
Use -Aleon to enable binutils sparc-leon architecture. The leon-arch
binutils GAS has umul/smul and casa enabled.
---
gcc/config/sparc/sparc.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index e0db816..94e5887 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -314,7 +314,7 @@ extern enum cmodel sparc_cmodel;
#if TARGET_CPU_DEFAULT == TARGET_CPU_leon
#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
-#define ASM_CPU32_DEFAULT_SPEC ""
+#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
#endif
#endif
@@ -403,7 +403,7 @@ extern enum cmodel sparc_cmodel;
/* Override in target specific files. */
#define ASM_CPU_SPEC "\
-%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
+%{mcpu=sparclet:-Asparclet} %{mcpu=leon:-Aleon} %{mcpu=tsc701:-Asparclet} \
%{mcpu=sparclite:-Asparclite} \
%{mcpu=sparclite86x:-Asparclite} \
%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
--
1.6.4.1
>From a0a9021cf3280ebf4df79cb6692366c55e507d25 Mon Sep 17 00:00:00 2001
From: Konrad Eisele <kon...@gaisler.com>
Date: Fri, 21 Oct 2011 13:32:42 +0200
Subject: [PATCH 1/1] sparc leon: add leon architecture to GAS
Add -Aleon architecture selection to GAS. -Aleon supports umul/smul and
[casa,casl].
---
gas/config/tc-sparc.c | 3 ++-
gas/configure.tgt | 6 +++++-
include/opcode/sparc.h | 1 +
opcodes/sparc-opc.c | 16 +++++++++-------
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 77fda56..47f4386 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -221,7 +221,7 @@ static void output_insn (const struct sparc_opcode *, struct sparc_it *);
for this use. That table is for opcodes only. This table is for opcodes
and file formats. */
-enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
+enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
v8plusa, v9, v9a, v9b, v9_64};
static struct sparc_arch {
@@ -246,6 +246,7 @@ static struct sparc_arch {
{ "sparcima", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_IMA },
{ "sparcvis3", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC },
{ "sparcvis3r", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU },
+ { "leon", "leon", leon, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
{ "sparclet", "sparclet", sparclet, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
{ "sparclite", "sparclite", sparclite, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
{ "sparc86x", "sparclite", sparc86x, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
diff --git a/gas/configure.tgt b/gas/configure.tgt
index a171a32..7b1f7e8 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -79,7 +79,11 @@ case ${cpu} in
sparc86x*) cpu_type=sparc arch=sparc86x ;;
sparclet*) cpu_type=sparc arch=sparclet ;;
sparclite*) cpu_type=sparc arch=sparclite ;;
- sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
+ sparc*)
+ case ${vendor} in
+ leon*) cpu_type=sparc arch=leon ;;
+ *) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
+ esac ;;
v850*) cpu_type=v850 ;;
x86_64*) cpu_type=i386 arch=x86_64;;
xtensa*) cpu_type=xtensa arch=xtensa ;;
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 7ae3641..2283a93 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -42,6 +42,7 @@ enum sparc_opcode_arch_val
SPARC_OPCODE_ARCH_V6 = 0,
SPARC_OPCODE_ARCH_V7,
SPARC_OPCODE_ARCH_V8,
+ SPARC_OPCODE_ARCH_LEON,
SPARC_OPCODE_ARCH_SPARCLET,
SPARC_OPCODE_ARCH_SPARCLITE,
/* V9 variants must appear last. */
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index a2096c5..cb19844 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -33,6 +33,7 @@
#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
+#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
@@ -56,6 +57,7 @@
recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B)
+#define leon (MASK_LEON)
#define sparclet (MASK_SPARCLET)
#define sparclite (MASK_SPARCLITE)
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
@@ -76,6 +78,7 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
{ "v6", MASK_V6 },
{ "v7", MASK_V6 | MASK_V7 },
{ "v8", MASK_V6 | MASK_V7 | MASK_V8 },
+ { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON },
{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
/* ??? Don't some v8 priviledged insns conflict with v9? */
@@ -1668,9 +1671,8 @@ EFPOP2_2 ("efcmpes", 0x055, "e,f"),
{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
/* sparclet specific insns */
-
-COMMUTEOP ("umac", 0x3e, sparclet),
-COMMUTEOP ("smac", 0x3f, sparclet),
+COMMUTEOP ("umac", 0x3e, sparclet|MASK_LEON),
+COMMUTEOP ("smac", 0x3f, sparclet|MASK_LEON),
COMMUTEOP ("umacd", 0x2e, sparclet),
COMMUTEOP ("smacd", 0x2f, sparclet),
COMMUTEOP ("umuld", 0x09, sparclet),
@@ -1721,8 +1723,8 @@ SLCBCC("cbnefr", 15),
#undef SLCBCC2
#undef SLCBCC
-{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
-{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
+{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9|MASK_LEON },
+{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9|MASK_LEON },
{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
@@ -1732,8 +1734,8 @@ SLCBCC("cbnefr", 15),
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
-{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
-{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
+{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9|MASK_LEON }, /* casa [rs1]ASI_P,rs2,rd */
+{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9|MASK_LEON }, /* casa [rs1]ASI_P_L,rs2,rd */
{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
--
1.6.4.1
