On 23/10/11 22:21, Richard Henderson wrote:
On 10/21/2011 05:49 PM, paul_kon...@dell.com wrote:
There are lots of parts of the compiler that don't optimize well when an insn
has more than one output. For the normal insn, just clobber the flags; don't
include a second SET.
Yes, but... isn't the whole point of CC modeling that you can take advantage of
the CC left around by an instruction? Typically in machines with condition
codes, you can eliminate test instructions (compare with zero) if the previous
instruction has that variable as its output. But if we're discouraged from
writing insns with CC outputs as normal practice, and if the compiler doesn't
handle such constructs well in optimization, what then?
The solution is to have *two* insn patterns, one with a set of the flags
and one with only a clobber. Have a look through i386.md and
how the flags register is handled there.
In version 4.6.1, i386.md, I see things like:
(define_insn "addqi3_cc"
[(set (reg:CC FLAGS_REG)
(unspec:CC
[(match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qn,qm")]
UNSPEC_ADD_CARRY))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
"add{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
This seems to be exactly what we are doing. I can't see where there are
separate rules for the flags register.
--
PMatos
