On Fri, 12 Aug 2011, Rohit Arul Raj wrote: > On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarul...@gmail.com> > wrote: > > Hello All, > > > > I am working on 32-bit target with gcc 4.6.0. I need some help on the > > following: > > > > For my target, If my CCR register is set, all the arithmetic > > instructions update the CC register else the don't update.
So you have a control register called CCR and a status register called CC? > > Setting the CCR register is done by a built-in function. Why is this user-controllable? My first thought is that this is misguided. Is this just a sketch or do you already have code using it? > > Can any one help how to proceed with this? or any other target where a > > similar case has been implemented? > > > > Thanks, > > Rohit > > > > Adding more info: > > Note: There is 2 cycle latency between compare and branch instructions. > > A) Without CCR register being set. > > cmp insn > branch insn > > Here i can insert any arithmetic instruction e.g. 'addsi' > in-between 'cmp' and 'branch' as the CC register doesn't get modified. Assuming that you can indeed emit reasonable code for compares and conditional branches without the "CCR register" set to the do-not-update state, I'd suggest you implement that. Forget about the builtin; don't implement it. Some time later, when you're sufficiently acquinted with gcc internals, maybe improve the generated code using the always-update state if you can indeed spot generated code that could be improved that way. Don't do this for at least a few months. If there is no such code, forget about the CCR=always-update state. In either case, never mention (cc0) in your .md file. brgds, H-P
