On Friday 27 June 2008, Julian Brown wrote: > On Fri, 27 Jun 2008 15:52:22 +0530 > > "Mohamed Shafi" <[EMAIL PROTECTED]> wrote: > > If the condition in the 'if' instruction is satisfied the processor > > will execute the next instruction or it will replace with a nop. So > > this means that i can instructions similar to: > > > > if eq Rx, Ry > > add Rx, Ry > > add Rx, 2 > > > > Will it be possible to implement this in the Gcc backend ? > > Does any other targets have similar instructions? > > This is very much like (a simpler version of) the ARM Thumb-2 IT > instruction. Look how config/arm/thumb2.md handles that. I think the > basic idea should be that you should define conditional instruction > patterns which emit assembly for both instructions simultaneously.
Not quite. For Thumb-2 we describe most instruction as having conditional variants using define_cond_exec. Then arrange for the necessary IfThen instructions to be generated via ASM_OUTPUT_OPCODE. Multiple assembly instructions from the same pattern are either a historical leftover, or when it's inconvenient to describe the operation with proper cond_exec RTL. Thumb-2 is a bit different to the machine described above because because the conditional execution is based on the condition code register, with the comparison occurring as a separate instruction, and the IT instruction can skip multiple subsequent instructions. I'd expect the same technique to be applicable though. Paul
