Hello all, For a port that i am working on has this particular addressing mode
load Rd, Ra[offset] store Rs, Ra[offset] For the above two instructions base register Ra should be an even register. This i have implemented using the macros REGNO_OK_FOR_BASE_P and BASE_REG_CLASS by creating a class with only even registers. For the source or the destination register Rd/Ra, the restriction is that it should be one more than the base register . So the following instructions are valid: load R5, R4[4] store R11, R10[2] while the following ones are wrong: load R8, R6[4] store R3, R8[2] I am not sure how to implement this in the back-end. Can anyone give me any ideas? Regards, Shafi
