Paolo Bonzini wrote:
SPE has patterns for
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
for example.
What are they trying to do? It's dubious for a number of reasons:
- SUBREG in the instruction pattern means that we'll eventually end up
with SUBREG of a hard register
- Any insn that matches this pattern would also match movsi
- There shouldn't really be multiple movsi patterns
Bernd
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