Nick, > I thought that L2 caches on the Opteron communicated by I > assume by your > response the Opteron memory controller doesn't allow cache > propagation, > instead invalidates the cache entries read (assuming again the write > entries are handled differently).
You're half right. The caches on the same processor do have a fast path between them, but the fact still remains that an L2 cache miss plus the cache coherency protocol overhead is far slower than an L2 cache hit. Bottom line: process migration is bad. HTH -- _______________________________________________________ Evandro Menezes AMD Austin, TX
