On Fri, Jan 19, 2007 at 05:10:27PM -0700, Sean D'Epagnier wrote:
> I am using gcc 3.3.5 with the latest m68hc1x patches to compile programs for a
> 9s12 processor, and cc1 calls abort when compiling the following code:
It would be most useful to have the exact error message. I'm guessing
that the problem here is an unrecognizable instruction.
> It looks like somewhere before generating rtl in the second case, it split
> the instruction
> as this architecture cannot handle the second instruction in the first case.
> xor behaves
> similarly to or and works as well.
>
> I am trying to find out what part of gcc to look in so I can make the change
> so that the and
> instruction is handled the same way.
I think the andhi3 expander (m68hc11.md) is at fault. Compare the
predicates for operand 2 with the ones for iorhi3 and xorhi3:
(define_expand "andhi3"
[(set (match_operand:HI 0 "register_operand" "")
(and:HI (match_operand:HI 1 "register_operand" "")
(match_operand:HI 2 "general_operand" "")))]
""
"")
(define_expand "iorhi3"
[(set (match_operand:HI 0 "register_operand" "")
(ior:HI (match_operand:HI 1 "register_operand" "")
(match_operand:HI 2 "splitable_operand" "")))]
""
"")
(define_insn "xorhi3"
[(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
(xor:HI (match_operand:HI 1 "splitable_operand" "%0,0,0")
(match_operand:HI 2 "splitable_operand" "im,!u*A,!ium*A")))]
""
...
I'd try changing operand 2 of andhi3 from general_operand to
splitable_operand, because none of the andhi3 insn patterns seem to match
(set (reg:HI) (and:HI (reg:HI) (mem:HI (mem:HI ...)))). In particular,
*andhi3_gen needs operand 2 to be a splitable_operand, which (mem:HI (mem:HI
...)) is not.
--
Rask Ingemann Lambertsen
