Dave Korn writes:
>Is it just me, or does anyone else get this? I objdump'd and diff'd the
>stage2 and stage3 versions of cfg.o and it seems to have developed a habit of
>inserting 'shrd'/'shld' opcodes:
It looks to me like the stage3 version with the shrd/shld is correct
and it's that stage2 version that's missing opcodes. In both versions
the source and destination of the shift are a 64-bit pair of registers,
but the stage2 version uses 32-bit shifts, while the stage3 version uses
64-bit shitfs. The code in the first chunk looks like it's the result
of the expansion of the RDIV macro with the dividend being a "gcov_type"
value and the divisor being 65536. It looks like "gcov_type" is 64-bits,
so it should be using 64-bit arithmetic.
> although disturbingly enough there's a missing 'lea' too:
It's a NOP. Probably inserted by the assembler because of an alignment
directive.
Ross Ridge
