The CPU ,I am porting GCC to , has PUSH instruction for half-word (byte) and PUSH instruction for word as well.
GCC is using them well, until I was told to add a command-line option which allows GCC to align on word.
It has been done, however, there samoe problems. GCC generates following code:
PUSH AL ; AL is 8-bit reister INC S ; increment stack pointer
This is correct code, but it is longer than
PUSH A ; where A is 16 bit register
And if RAM does not allow access on ODD addresses.
I have define following macros as follows
/ *tm.h */
#define PARM_BOUNDARY (TARGET_STACK_BYTE_ALLIGN?BITS_PER_WORD / 2: BITS_PER_WORD)
#define STACK_BOUNDARY ((TARGET_STACK_BYTE_ALLIGN?BITS_PER_WORD / 2: BITS_PER_WORD))
/***/
In .md file have defined
(define_expand "pushqi"
[
(set (mem:QI (post_inc (reg:HI S_HREG)))
(match_operand:QI 0 "general_operand" "")
)
]
""
""
)(define_insn "*pushqi"
[(set (mem:QI (post_inc (reg:HI S_HREG)))
(match_operand:QI 0 "general_operand" "b"))]
"TARGET_STACK_BYTE_ALLIGN"
"push\t%0\t; *pushqi"
[(set_attr "cc" "none")]
)(define_insn "*pushqi_word_aligned"
[(set (mem:QI (post_inc (reg:HI S_HREG)))
(match_operand:QI 0 "general_operand" "b"))]
"!TARGET_STACK_BYTE_ALLIGN"
"#"
[(set_attr "cc" "none")]
)(define_split
[(set (mem:QI (post_inc (reg:HI S_HREG)))
(match_operand:QI 0 "general_operand" "b"))]
"!TARGET_STACK_BYTE_ALLIGN"
[
(set (match_dup 1)
(match_dup 0)
)
(set (mem:HI (post_inc (reg:HI S_HREG)))
(match_dup 1)
)
]
"
operands[1] = gen_rtx(REG, HImode, A_HREG);
"
)The asm code I expect this RTL to generate is PUSH A
BUT instead of that it generates
PUSH A ; stack is even INC S ; incorrect (the stack is ODD)
What am I doing wrong ? Can somebody tell me how to solve this problem ?
Regards Petar Penchev Software engineer
