On Friday 15 April 2005 13:33, Petar Penchev wrote: > Hello All, > The CPU ,I am porting GCC to , has PUSH instruction for half-word (byte) > and PUSH instruction for word as well. > GCC is using them well, until I was told to add a command-line option > which allows GCC to align on word. > It has been done, however, there samoe problems. GCC generates following > code: > > PUSH AL ; AL is 8-bit reister > INC S ; increment stack pointer > > This is correct code, but it is longer than > > PUSH A ; where A is 16 bit register<...>
Obviously this only works on little-endian targets. <...> > [(set (mem:QI (post_inc (reg:HI S_HREG))) > (match_operand:QI 0 "general_operand" "b"))] > "!TARGET_STACK_BYTE_ALLIGN" > [ > (set (match_dup 1) > (match_dup 0) > ) > (set (mem:HI (post_inc (reg:HI S_HREG))) > (match_dup 1) > ) > ] > " > operands[1] = gen_rtx(REG, HImode, A_HREG); > " > ) A post_inc increments by the size of the memory access. A define_split is supposed to replace one insn by multiple insns that do the same thing. You're replacing a byte increment with a word increment. You could try adding a define_peephole2 that turns push al; inc S into push a. Paul
