On Thu, Apr 17, 2014 at 4:00 PM, Michael Matz wrote: >> And to have sth that TER not immediately un-does we have >> to disable TER which conveniently happens for coalesced >> SSA names. > > So, instead TER should be improved to not disturb the incoming instruction > order (except where secondary effects of expanding larger trees can be > had). Changing the coalescing set to disable some bad parts in a later > pass doesn't sound very convincing :)
IMHO TER should be improved to *do* disturb the order of the incoming instructions, to reduce register pressure. There are test cases I've looked at (pathological cases, I'll admit) where TER forwarded loads to stores and blew up register pressure. Alternatively: Do what has to be done to enable sched1 for ix86/x86_64... Ciao! Steven
