Hi, On Thu, 17 Apr 2014, Richard Biener wrote:
> The patch below increases the number of coalescs we attempt > to also cover unary and binary operations. This is not usually a good idea if not mitigated by things like register pressure measurement and using target properties to determine if it's a two- or three-address instruction. It increases register pressure and naturally generates multiple-def pseudos which aren't liked by some of the RTL passes. It will lead to fewer pseudos, so there's a positive side. > Now the question is what does this tell us? Not re-using the same > pseudo as op and target is always better? No, it tells us that tree-ssa-coalesce is too early for such coalescing. The register allocator is the right spot (or instruction selection if we had that), and it's done there. > And to have sth that TER not immediately un-does we have > to disable TER which conveniently happens for coalesced > SSA names. So, instead TER should be improved to not disturb the incoming instruction order (except where secondary effects of expanding larger trees can be had). Changing the coalescing set to disable some bad parts in a later pass doesn't sound very convincing :) Ciao, Michael.
