On Tue, May 21, 2013 at 5:49 PM, Sandra Loosemore <san...@codesourcery.com> wrote: > On 05/20/2013 03:20 PM, David Edelsohn wrote: >> >> This seems like a reasonable change and *should* improve performance, >> but what is the actual effect on performance, especially recent POWER >> processors? We have had some recent cases where increased alignment >> hurt performance because of secondary effects on spilling. > > > I've poked around a bit. We seem to have no suitable Altivec hardware for > bare-metal benchmarking (we do simulator testing for -te600 instead), but we > have a Freescale 8641D board available for GNU/Linux. It's about 5 years old > so I don't know if it qualifies as a sufficiently recent processor? (Like I > said before, we can't justify spending a lot of time trying to get this > patch on mainline, and I especially don't want to waste time setting up > benchmarking that would not be useful anyway.)
There are three issues here: 1) Someone in the LTC toolchain team needs to benchmark this patch on POWER7. 2) We need to clarify how the patch affects the ABI because it cannot break the ABI. 3) Please stop saying that you cannot justify trying to get the patch in mainline. Other developers have pointed out how the patch may be incorrect. Do you want to deliver a broken compiler to CodeSourcery's customers? The comment sets a bad tone for engaging with the GCC community. Thanks, David
