Although we have handled the vl of XTheadVector correctly in the
expand phase and predicates, the results show that the work is
still insufficient.
In the curr_insn_transform function, the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128]
A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(reg:DI 209)
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 143 [ _xx ])
(mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128] A32])))
(expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
(nil)))
to
(insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0
S[128, 128] A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(const_int 1 [0x1])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
(mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0 S[128, 128]
A32])))
(nil))
Looking at the log for the reload pass, it is found that "Changing pseudo 209 in
operand 3 of insn 69 on equiv 0x1".
It converts the vl operand in insn from the expected register(reg:DI 209) to the
constant 1(const_int 1 [0x1]).
This conversion occurs because, although the predicate for the vl operand is
restricted by "vector_length_operand" in the pattern, the constraint is still
"rK", which allows the transformation.
The issue is that changing the "rK" constraint to "rJ" for the constraint of vl
operand in the pattern would prevent this conversion, But unfortunately this
will
conflict with RVV (RISC-V Vector Extension).
Based on the review's recommendations, the best solution for now is to create
a new constraint to distinguish between RVV and XTheadVector, which is exactly
what this patch does.
PR 116593
gcc/ChangeLog:
* config/riscv/constraints.md (vl): New.
* config/riscv/thead-vector.md: Replacing rK with rvl.
* config/riscv/vector.md: Likewise.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/rvv.exp: Enable testsuite of XTheadVector.
* g++.target/riscv/rvv/xtheadvector/pr116593.C: New test.
Reported-by: nihui <shuizhuyuan...@gmail.com>
---
gcc/config/riscv/constraints.md | 6 +
gcc/config/riscv/thead-vector.md | 18 +-
gcc/config/riscv/vector.md | 476 +++++++++---------
gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 3 +
.../riscv/rvv/xtheadvector/pr116593.C | 47 ++
5 files changed, 303 insertions(+), 247 deletions(-)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index f25975dc0208..ba3c6e6a4c44 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -209,6 +209,12 @@ (define_constraint "vk"
(and (match_code "const_vector")
(match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))
+(define_constraint "vl"
+ "A uimm5 for Vector or zero for XTheadVector."
+ (and (match_code "const_int")
+ (ior (match_test "!TARGET_XTHEADVECTOR && satisfies_constraint_K (op)")
+ (match_test "TARGET_XTHEADVECTOR && satisfies_constraint_J (op)"))))
+
(define_constraint "Wc0"
"@internal
A constraint that matches a vector of immediate all zeros."
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5fe9ba08c4eb..5a02debdd207 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -108,7 +108,7 @@ (define_insn_and_split "@pred_th_whole_mov<mode>"
[(set (match_operand:V_VLS_VT 0 "reg_or_mem_operand" "=vr,vr, m")
(unspec:V_VLS_VT
[(match_operand:V_VLS_VT 1 "reg_or_mem_operand" " vr, m,vr")
- (match_operand 2 "vector_length_operand" " rK, rK, rK")
+ (match_operand 2 "vector_length_operand" "rvl,rvl,rvl")
(match_operand 3 "const_1_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)]
@@ -133,7 +133,7 @@ (define_insn_and_split "@pred_th_whole_mov<mode>"
[(set (match_operand:VB 0 "reg_or_mem_operand" "=vr,vr, m")
(unspec:VB
[(match_operand:VB 1 "reg_or_mem_operand" " vr, m,vr")
- (match_operand 2 "vector_length_operand" " rK, rK, rK")
+ (match_operand 2 "vector_length_operand" "rvl,rvl,rvl")
(match_operand 3 "const_1_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)]
@@ -161,7 +161,7 @@ (define_insn_and_split "*pred_th_mov<mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1,
Wc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -210,7 +210,7 @@ (define_insn_and_split
"*pred_mov_width<vlmem_op_attr><mode>"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1,
vm, vmWc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
@@ -239,7 +239,7 @@ (define_insn "@pred_store_width<vlmem_op_attr><mode>"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP)
@@ -257,7 +257,7 @@ (define_insn "@pred_strided_load_width<vlmem_op_attr><mode>"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
(match_operand 8 "const_int_operand" " i, i, i")
@@ -277,7 +277,7 @@ (define_insn
"@pred_strided_store_width<vlmem_op_attr><mode>"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP)
@@ -296,7 +296,7 @@ (define_insn "@pred_indexed_load_width<vlmem_op_attr><mode>"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -317,7 +317,7 @@ (define_insn
"@pred_indexed_<vlmem_order_attr>store_width<vlmem_op_attr><mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 243f3f76d28a..cf22b39d6cb3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1708,7 +1708,7 @@ (define_insn_and_split "*vec_duplicate<mode>"
(define_insn "@vsetvl<mode>"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
+ (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
@@ -1754,7 +1754,7 @@ (define_insn "vsetvl_vtype_change_only"
;; in vsetvl instruction pattern.
(define_insn "@vsetvl_discard_result<mode>"
[(set (reg:SI VL_REGNUM)
- (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
+ (unspec:SI [(match_operand:P 0 "vector_length_operand" "rvl")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
@@ -1776,7 +1776,7 @@ (define_insn "@vsetvl_discard_result<mode>"
;; such pattern can allow us gain benefits of these optimizations.
(define_insn_and_split "@vsetvl<mode>_no_side_effects"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
+ (unspec:P [(match_operand:P 1 "vector_length_operand" "rvl")
(match_operand 2 "const_int_operand" "i")
(match_operand 3 "const_int_operand" "i")
(match_operand 4 "const_int_operand" "i")
@@ -1901,7 +1901,7 @@ (define_insn_and_split "*pred_mov<mode>"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1,
vm, vmWc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -1932,7 +1932,7 @@ (define_insn "@pred_store<mode>"
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1955,7 +1955,7 @@ (define_insn_and_split "@pred_mov<mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1,
Wc1, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1981,7 +1981,7 @@ (define_insn "@pred_store<mode>"
(if_then_else:VB
(unspec:VB
[(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" "rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -1998,7 +1998,7 @@ (define_insn "@pred_merge<mode>"
[(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
(if_then_else:V_VLS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
@@ -2017,7 +2017,7 @@ (define_insn "@pred_merge<mode>_scalar"
[(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -2069,7 +2069,7 @@ (define_insn "*pred_merge<mode>_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -2089,7 +2089,7 @@ (define_insn "*pred_merge<mode>_extended_scalar"
[(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -2198,7 +2198,7 @@ (define_insn_and_split "*pred_broadcast<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,
vm, vm,Wc1,Wc1,Wb1,Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
@@ -2259,7 +2259,7 @@ (define_insn "*pred_broadcast<mode>_zvfh"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1, Wc1,
Wb1, Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl, rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i")
@@ -2282,7 +2282,7 @@ (define_insn "*pred_broadcast<mode>_zvfhmin"
(if_then_else:V_VLSF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand" " vm,
vm, Wc1, Wc1")
- (match_operand 4 "vector_length_operand" " rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,
rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i,
i, i, i")
(match_operand 6 "const_int_operand" " i,
i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i")
@@ -2305,7 +2305,7 @@ (define_insn "*pred_broadcast<mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_broadcast_mask_operand"
"Wc1,Wc1,Wb1,Wb1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i")
@@ -2329,7 +2329,7 @@ (define_insn "*pred_broadcast<mode>_zero"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_least_significant_set_mask_operand"
"Wb1, Wb1")
- (match_operand 4 "vector_length_operand" "
rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl, rvl")
(match_operand 5 "const_int_operand" "
i, i")
(match_operand 6 "const_int_operand" "
i, i")
(match_operand 7 "const_int_operand" "
i, i")
@@ -2349,7 +2349,7 @@ (define_insn "*pred_broadcast<mode>_imm"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1,
Wc1")
- (match_operand 4 "vector_length_operand" " rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl,
rvl")
(match_operand 5 "const_int_operand" " i,
i")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
@@ -2374,7 +2374,7 @@ (define_insn "@pred_strided_load<mode>"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm,
vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i, i")
@@ -2402,7 +2402,7 @@ (define_insn "@pred_strided_store<mode>"
[(match_operand:V_VLS 0 "memory_operand" " +m, m")
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2429,7 +2429,7 @@ (define_insn "@pred_indexed_<order>load<mode>_same_eew"
(if_then_else:VINDEXED
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2451,7 +2451,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x2_greater_eew"
(if_then_else:VEEWEXT2
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2472,7 +2472,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x4_greater_eew"
(if_then_else:VEEWEXT4
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2493,7 +2493,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x8_greater_eew"
(if_then_else:VEEWEXT8
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -2515,7 +2515,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x2_smaller_eew"
(if_then_else:VEEWTRUNC2
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i")
@@ -2536,7 +2536,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x4_smaller_eew"
(if_then_else:VEEWTRUNC4
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i")
@@ -2557,7 +2557,7 @@ (define_insn
"@pred_indexed_<order>load<mode>_x8_smaller_eew"
(if_then_else:VEEWTRUNC8
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i, i")
@@ -2578,7 +2578,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2595,7 +2595,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2612,7 +2612,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2629,7 +2629,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2646,7 +2646,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2663,7 +2663,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2680,7 +2680,7 @@ (define_insn
"@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -2710,7 +2710,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm,
vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,
rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i, i, i, i, i, i, i")
@@ -2746,7 +2746,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK,
rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i, i,
i, i")
@@ -2767,7 +2767,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2788,7 +2788,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2809,7 +2809,7 @@ (define_insn "@pred_sub<mode>_reverse_scalar"
(if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2865,7 +2865,7 @@ (define_insn "*pred_<optab><mode>_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2886,7 +2886,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2941,7 +2941,7 @@ (define_insn "*pred_<optab><mode>_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -2962,7 +2962,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3017,7 +3017,7 @@ (define_insn "*pred_sub<mode>_reverse_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3038,7 +3038,7 @@ (define_insn "*pred_sub<mode>_extended_reverse_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3061,7 +3061,7 @@ (define_insn "@pred_mulh<v_su><mode>"
(if_then_else:VFULLI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3081,7 +3081,7 @@ (define_insn "@pred_mulh<v_su><mode>_scalar"
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3135,7 +3135,7 @@ (define_insn "*pred_mulh<v_su><mode>_scalar"
(if_then_else:VFULLI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3156,7 +3156,7 @@ (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
(if_then_else:VFULLI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -3178,7 +3178,7 @@ (define_insn "@pred_adc<mode>"
[(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
(if_then_else:VI
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
@@ -3202,7 +3202,7 @@ (define_insn "@pred_sbc<mode>"
[(set (match_operand:VI 0 "register_operand" "=vd,vd")
(if_then_else:VI
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3226,7 +3226,7 @@ (define_insn "@pred_adc<mode>_scalar"
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:VI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3251,7 +3251,7 @@ (define_insn "@pred_sbc<mode>_scalar"
[(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
(if_then_else:VI_QHS
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3309,7 +3309,7 @@ (define_insn "*pred_adc<mode>_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3334,7 +3334,7 @@ (define_insn "*pred_adc<mode>_extended_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3393,7 +3393,7 @@ (define_insn "*pred_sbc<mode>_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3418,7 +3418,7 @@ (define_insn "*pred_sbc<mode>_extended_scalar"
[(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
(if_then_else:VI_D
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" "rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -3448,7 +3448,7 @@ (define_insn "@pred_madc<mode>"
(match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3468,7 +3468,7 @@ (define_insn "@pred_msbc<mode>"
(match_operand:VI 2 "register_operand" " vr, 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl,rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3489,7 +3489,7 @@ (define_insn "@pred_madc<mode>_scalar"
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3510,7 +3510,7 @@ (define_insn "@pred_msbc<mode>_scalar"
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3560,7 +3560,7 @@ (define_insn "*pred_madc<mode>_scalar"
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3582,7 +3582,7 @@ (define_insn "*pred_madc<mode>_extended_scalar"
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
@@ -3632,7 +3632,7 @@ (define_insn "*pred_msbc<mode>_scalar"
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3654,7 +3654,7 @@ (define_insn "*pred_msbc<mode>_extended_scalar"
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(match_operand:<VM> 3 "register_operand" " vm, vm")
(unspec:<VM>
- [(match_operand 4 "vector_length_operand" " rK, rK")
+ [(match_operand 4 "vector_length_operand" "rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
@@ -3673,7 +3673,7 @@ (define_insn "@pred_madc<mode>_overflow"
(match_operand:VI 1 "register_operand" " %0, vr, vr")
(match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK, rK")
+ [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 4 "const_int_operand" " i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3692,7 +3692,7 @@ (define_insn "@pred_msbc<mode>_overflow"
(match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
(match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
+ [(match_operand 3 "vector_length_operand" " rvl, rvl, rvl, rvl")
(match_operand 4 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3712,7 +3712,7 @@ (define_insn "@pred_madc<mode>_overflow_scalar"
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3732,7 +3732,7 @@ (define_insn "@pred_msbc<mode>_overflow_scalar"
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_QHS 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3780,7 +3780,7 @@ (define_insn "*pred_madc<mode>_overflow_scalar"
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3801,7 +3801,7 @@ (define_insn "*pred_madc<mode>_overflow_extended_scalar"
(match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3849,7 +3849,7 @@ (define_insn "*pred_msbc<mode>_overflow_scalar"
(match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3870,7 +3870,7 @@ (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
(match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 1 "register_operand" " 0, vr"))
(unspec:<VM>
- [(match_operand 3 "vector_length_operand" " rK, rK")
+ [(match_operand 3 "vector_length_operand" "rvl, rvl")
(match_operand 4 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
@@ -3894,7 +3894,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -3927,7 +3927,7 @@ (define_insn "@pred_<optab><mode>_vf2"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3947,7 +3947,7 @@ (define_insn "@pred_<optab><mode>_vf4"
(if_then_else:VQEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3967,7 +3967,7 @@ (define_insn "@pred_<optab><mode>_vf8"
(if_then_else:VOEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -3987,7 +3987,7 @@ (define_insn
"@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4009,7 +4009,7 @@ (define_insn
"@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scal
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4032,7 +4032,7 @@ (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4053,7 +4053,7 @@ (define_insn "@pred_single_widen_add<any_extend:su><mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4074,7 +4074,7 @@ (define_insn
"@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -4096,7 +4096,7 @@ (define_insn
"@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -4119,7 +4119,7 @@ (define_insn
"@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK,rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -4142,7 +4142,7 @@ (define_insn "@pred_widen_mulsu<mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4164,7 +4164,7 @@ (define_insn "@pred_widen_mulsu<mode>_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -4188,7 +4188,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl,
rvl")
(match_operand 5 "const_int_operand" " i,
i")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
@@ -4224,7 +4224,7 @@ (define_insn "@pred_narrow_<optab><mode>"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,rK,
rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
@@ -4246,7 +4246,7 @@ (define_insn "@pred_narrow_<optab><mode>_scalar"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 8 "const_int_operand" " i,
i, i, i, i, i")
@@ -4269,7 +4269,7 @@ (define_insn "@pred_trunc<mode>"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
@@ -4305,7 +4305,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm,
vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK,
rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i, i,
i, i, i")
@@ -4334,7 +4334,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4355,7 +4355,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4409,7 +4409,7 @@ (define_insn "*pred_<optab><mode>_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4430,7 +4430,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4485,7 +4485,7 @@ (define_insn "*pred_<optab><mode>_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4506,7 +4506,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4528,7 +4528,7 @@ (define_insn "@pred_<sat_op><mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4551,7 +4551,7 @@ (define_insn "@pred_<sat_op><mode>_scalar"
(if_then_else:VI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4573,7 +4573,7 @@ (define_insn "@pred_<sat_op><mode>_scalar"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4631,7 +4631,7 @@ (define_insn "*pred_<sat_op><mode>_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4653,7 +4653,7 @@ (define_insn "*pred_<sat_op><mode>_extended_scalar"
(if_then_else:VI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -4677,7 +4677,7 @@ (define_insn "@pred_narrow_clip<v_su><mode>"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,rK,
rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl,rvl,rvl, rvl, rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i, i, i, i")
@@ -4700,7 +4700,7 @@ (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK, rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 7 "const_int_operand" " i,
i, i, i, i, i")
(match_operand 8 "const_int_operand" " i,
i, i, i, i, i")
@@ -4747,7 +4747,7 @@ (define_insn "*pred_cmp<mode>_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4771,7 +4771,7 @@ (define_insn "*pred_cmp<mode>"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4792,7 +4792,7 @@ (define_insn "*pred_cmp<mode>_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4829,7 +4829,7 @@ (define_insn "*pred_ltge<mode>_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4853,7 +4853,7 @@ (define_insn "*pred_ltge<mode>"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4874,7 +4874,7 @@ (define_insn "*pred_ltge<mode>_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -4912,7 +4912,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -4937,7 +4937,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -4959,7 +4959,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5022,7 +5022,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5047,7 +5047,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5069,7 +5069,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5090,7 +5090,7 @@ (define_insn
"*pred_cmp<mode>_extended_scalar_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -5116,7 +5116,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -5138,7 +5138,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -5306,7 +5306,7 @@ (define_insn "*pred_mul_plus<mode>_undef"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1,Wc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
@@ -5332,7 +5332,7 @@ (define_insn "*pred_madd<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5361,7 +5361,7 @@ (define_insn "*pred_macc<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5409,7 +5409,7 @@ (define_insn "*pred_madd<mode>_scalar"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5439,7 +5439,7 @@ (define_insn "*pred_macc<mode>_scalar"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5504,7 +5504,7 @@ (define_insn "*pred_madd<mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5535,7 +5535,7 @@ (define_insn "*pred_macc<mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5588,7 +5588,7 @@ (define_insn "*pred_minus_mul<mode>_undef"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
@@ -5614,7 +5614,7 @@ (define_insn "*pred_nmsub<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5643,7 +5643,7 @@ (define_insn "*pred_nmsac<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5693,7 +5693,7 @@ (define_insn "*pred_nmsub<mode>_scalar"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5723,7 +5723,7 @@ (define_insn "*pred_nmsac<mode>_scalar"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5788,7 +5788,7 @@ (define_insn "*pred_nmsub<mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5819,7 +5819,7 @@ (define_insn "*pred_nmsac<mode>_extended_scalar"
(if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -5857,7 +5857,7 @@ (define_insn "@pred_widen_mul_plus<su><mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -5881,7 +5881,7 @@ (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -5906,7 +5906,7 @@ (define_insn "@pred_widen_mul_plussu<mode>"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -5930,7 +5930,7 @@ (define_insn "@pred_widen_mul_plussu<mode>_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -5955,7 +5955,7 @@ (define_insn "@pred_widen_mul_plusus<mode>_scalar"
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -5997,7 +5997,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6017,7 +6017,7 @@ (define_insn "@pred_n<optab><mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6038,7 +6038,7 @@ (define_insn "@pred_<optab>not<mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6059,7 +6059,7 @@ (define_insn "@pred_not<mode>"
(if_then_else:VB_VLS
(unspec:VB_VLS
[(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" "rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -6080,7 +6080,7 @@ (define_insn "@pred_popcount<VB_VLS:mode><P:mode>"
[(and:VB_VLS
(match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1")
(match_operand:VB_VLS 2 "register_operand" " vr"))
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
@@ -6097,7 +6097,7 @@ (define_insn "@pred_ffs<VB:mode><P:mode>"
[(and:VB
(match_operand:VB 1 "vector_mask_operand" "vmWc1")
(match_operand:VB 2 "register_operand" " vr"))
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
@@ -6112,7 +6112,7 @@ (define_insn "@pred_<misc_op><mode>"
(if_then_else:VB
(unspec:VB
[(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -6130,7 +6130,7 @@ (define_insn "@pred_iota<mode>"
(if_then_else:VI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -6149,7 +6149,7 @@ (define_insn "@pred_series<mode>"
(if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 3 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 4 "const_int_operand" " i, i, i, i")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
@@ -6177,7 +6177,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6201,7 +6201,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6221,7 +6221,7 @@ (define_insn "@pred_<ieee_fmaxmin_op><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6242,7 +6242,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6267,7 +6267,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6288,7 +6288,7 @@ (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6310,7 +6310,7 @@ (define_insn "@pred_<optab><mode>_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6335,7 +6335,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6360,7 +6360,7 @@ (define_insn "@pred_<copysign><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6380,7 +6380,7 @@ (define_insn "@pred_ncopysign<mode>"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6401,7 +6401,7 @@ (define_insn "@pred_<copysign><mode>_scalar"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6422,7 +6422,7 @@ (define_insn "@pred_ncopysign<mode>_scalar"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -6475,7 +6475,7 @@ (define_insn "*pred_mul_<optab><mode>_undef"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
- (match_operand 6 "vector_length_operand" " rK,rK, rK, rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
@@ -6505,7 +6505,7 @@ (define_insn "*pred_<madd_msub><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6538,7 +6538,7 @@ (define_insn "*pred_<macc_msac><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6594,7 +6594,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6628,7 +6628,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6687,7 +6687,7 @@ (define_insn "*pred_mul_neg_<optab><mode>_undef"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
- (match_operand 6 "vector_length_operand" " rK,rK, rK, rK")
+ (match_operand 6 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
@@ -6718,7 +6718,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6752,7 +6752,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6810,7 +6810,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6845,7 +6845,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -6891,7 +6891,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -6918,7 +6918,7 @@ (define_insn "@pred_<optab><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -6941,7 +6941,7 @@ (define_insn "@pred_<misc_op><mode>"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -6960,7 +6960,7 @@ (define_insn "@pred_<misc_frm_op><mode>"
(if_then_else:VF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -6983,7 +6983,7 @@ (define_insn "@pred_class<mode>"
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7011,7 +7011,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7037,7 +7037,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7064,7 +7064,7 @@ (define_insn "@pred_single_widen_add<mode>"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7089,7 +7089,7 @@ (define_insn "@pred_single_widen_sub<mode>"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7114,7 +7114,7 @@ (define_insn
"@pred_single_widen_<plus_minus:optab><mode>_scalar"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 5 "vector_length_operand"
"rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
(match_operand 8 "const_int_operand" " i, i, i,
i")
@@ -7147,7 +7147,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7175,7 +7175,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7204,7 +7204,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7233,7 +7233,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7288,7 +7288,7 @@ (define_insn "*pred_cmp<mode>"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -7308,7 +7308,7 @@ (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7332,7 +7332,7 @@ (define_insn "*pred_cmp<mode>_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl, rvl, rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
@@ -7370,7 +7370,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" "rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7395,7 +7395,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
@@ -7417,7 +7417,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(if_then_else:<VM>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "
0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK,
rK, rK, rK")
+ (match_operand 6 "vector_length_operand" " rvl, rvl,
rvl, rvl, rvl")
(match_operand 7 "const_int_operand" " i, i,
i, i, i")
(match_operand 8 "const_int_operand" " i, i,
i, i, i")
(reg:SI VL_REGNUM)
@@ -7444,7 +7444,7 @@ (define_insn "@pred_merge<mode>_scalar"
[(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
(if_then_else:V_VLSF
(unspec:<VM>
- [(match_operand 5 "vector_length_operand" " rK,rK")
+ [(match_operand 5 "vector_length_operand" "rvl,rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -7472,7 +7472,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7495,7 +7495,7 @@ (define_insn "@pred_<fix_cvt><mode>"
(if_then_else:<VCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7514,7 +7514,7 @@ (define_insn "@pred_<float_cvt><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 5 "const_int_operand" " i, i, i, i")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
@@ -7544,7 +7544,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
(if_then_else:VWCONVERTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7567,7 +7567,7 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(if_then_else:VWCONVERTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7586,7 +7586,7 @@ (define_insn "@pred_widen_<float_cvt><mode>"
(if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7605,7 +7605,7 @@ (define_insn "@pred_extend<mode>"
(if_then_else:VWEXTF_ZVFHMIN
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7631,7 +7631,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK,
rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 6 "const_int_operand" " i, i, i,
i, i, i")
(match_operand 7 "const_int_operand" " i, i, i,
i, i, i")
@@ -7655,7 +7655,7 @@ (define_insn "@pred_narrow_<fix_cvt><mode>"
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i,
i, i")
@@ -7674,7 +7674,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
(if_then_else:<VNCONVERT>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK,
rK, rK")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl,
rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 6 "const_int_operand" " i, i, i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i, i, i,
i, i")
@@ -7698,7 +7698,7 @@ (define_insn "@pred_trunc<mode>"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -7722,7 +7722,7 @@ (define_insn "@pred_rod_trunc<mode>"
(if_then_else:<V_DOUBLE_TRUNC>
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK,
rK, rK, rK, rK")
+ (match_operand 4 "vector_length_operand"
"rvl,rvl,rvl,rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 6 "const_int_operand" " i, i,
i, i, i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i, i, i")
@@ -7758,7 +7758,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -7780,7 +7780,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7801,7 +7801,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -7823,7 +7823,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7844,7 +7844,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(reg:SI VL_REGNUM)
@@ -7866,7 +7866,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
@@ -7887,7 +7887,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7913,7 +7913,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -7938,7 +7938,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK,
rK")
+ (match_operand 5 "vector_length_operand" " rvl,
rvl")
(match_operand 6 "const_int_operand" " i,
i")
(match_operand 7 "const_int_operand" " i,
i")
(match_operand 8 "const_int_operand" " i,
i")
@@ -7964,7 +7964,7 @@ (define_insn "@pred_<reduc_op_pat_name><mode>"
(unspec:<V_EXT_LMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
+ (match_operand 5 "vector_length_operand" " rvl")
(match_operand 6 "const_int_operand" " i")
(match_operand 7 "const_int_operand" " i")
(match_operand 8 "const_int_operand" " i")
@@ -8092,7 +8092,7 @@ (define_insn "@pred_slide<ud><mode>"
(unspec:V_VLS
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8112,7 +8112,7 @@ (define_insn "@pred_slide<ud><mode>"
(unspec:V_VLSI_QHS
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8156,7 +8156,7 @@ (define_insn "*pred_slide<ud><mode>"
(unspec:V_VLSI_D
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8175,7 +8175,7 @@ (define_insn "*pred_slide<ud><mode>_extended"
(unspec:V_VLSI_D
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8196,7 +8196,7 @@ (define_insn "@pred_slide<ud><mode>"
(unspec:V_VLSF
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
+ (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
@@ -8216,7 +8216,7 @@ (define_insn "@pred_gather<mode>"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8236,7 +8236,7 @@ (define_insn "@pred_gather<mode>_scalar"
(if_then_else:V_VLS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8257,7 +8257,7 @@ (define_insn "@pred_gatherei16<mode>"
(if_then_else:VEI16
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8278,7 +8278,7 @@ (define_insn "@pred_compress<mode>"
(unspec:V_VLS
[(unspec:<VM>
[(match_operand:<VM> 3 "register_operand" " vm, vm")
- (match_operand 4 "vector_length_operand" " rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl")
(match_operand 5 "const_int_operand" " i, i")
(match_operand 6 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
@@ -8318,7 +8318,7 @@ (define_insn "@pred_fault_load<mode>"
(if_then_else:V
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1,
Wc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK,
rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl,
rvl")
(match_operand 5 "const_int_operand" " i, i, i,
i")
(match_operand 6 "const_int_operand" " i, i, i,
i")
(match_operand 7 "const_int_operand" " i, i, i,
i")
@@ -8356,7 +8356,7 @@ (define_insn "@pred_unit_strided_load<mode>"
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 4 "vector_length_operand" " rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
@@ -8376,7 +8376,7 @@ (define_insn "@pred_unit_strided_store<mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 3 "vector_length_operand" " rvl")
(match_operand 4 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8393,7 +8393,7 @@ (define_insn "@pred_strided_load<mode>"
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 5 "vector_length_operand" " rK, rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
(match_operand 8 "const_int_operand" " i, i, i")
@@ -8414,7 +8414,7 @@ (define_insn "@pred_strided_store<mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8432,7 +8432,7 @@ (define_insn "@pred_fault_load<mode>"
(if_then_else:VT
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
- (match_operand 4 "vector_length_operand" " rK, rK, rK")
+ (match_operand 4 "vector_length_operand" " rvl, rvl, rvl")
(match_operand 5 "const_int_operand" " i, i, i")
(match_operand 6 "const_int_operand" " i, i, i")
(match_operand 7 "const_int_operand" " i, i, i")
@@ -8463,7 +8463,7 @@ (define_insn
"@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
(if_then_else:V1T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8484,7 +8484,7 @@ (define_insn
"@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
(if_then_else:V2T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8505,7 +8505,7 @@ (define_insn
"@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
(if_then_else:V4T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8526,7 +8526,7 @@ (define_insn
"@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
(if_then_else:V8T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8547,7 +8547,7 @@ (define_insn
"@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
(if_then_else:V16T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8568,7 +8568,7 @@ (define_insn
"@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
(if_then_else:V32T
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 5 "vector_length_operand" " rvl, rvl")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
@@ -8589,7 +8589,7 @@ (define_insn
"@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8606,7 +8606,7 @@ (define_insn
"@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8623,7 +8623,7 @@ (define_insn
"@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8640,7 +8640,7 @@ (define_insn
"@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8657,7 +8657,7 @@ (define_insn
"@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
@@ -8674,7 +8674,7 @@ (define_insn
"@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
(unspec:BLK
[(unspec:<VM>
[(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
- (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 4 "vector_length_operand" " rvl")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index e587c3e14404..1bd73cdbeed0 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -45,5 +45,8 @@ dg-runtest [lsort [glob -nocomplain
$srcdir/$subdir/base/*.C]] \
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.C]] \
+ "" $CFLAGS
+
# All done.
dg-finish
diff --git a/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
new file mode 100644
index 000000000000..cef5bec13e34
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/xtheadvector/pr116593.C
@@ -0,0 +1,47 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target {
rv32 } } } */
+/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target {
rv64 } } } */
+
+#include <math.h>
+#include <riscv_vector.h>
+#include <vector>
+
+static
+vfloat32m8_t atan2_ps (vfloat32m8_t a, vfloat32m8_t b, size_t vl)
+{
+ std::vector<float> tmpx (vl);
+ std::vector<float> tmpy (vl);
+ __riscv_vse32_v_f32m8 (tmpx.data (), a, vl);
+ __riscv_vse32_v_f32m8 (tmpy.data (), b, vl);
+ for (size_t i = 0; i < vl; i++)
+ {
+ tmpx[i] = atan2 (tmpx[i], tmpy[i]);
+ }
+ return __riscv_vle32_v_f32m8 (tmpx.data (), vl);
+}
+
+void
+atan2 (const float *x, const float *y, float *out, int size, int ch)
+{
+ for (int i = 0; i < ch; i++)
+ {
+ const float *xx = x + size * i;
+ const float *yy = y + size * i;
+ float *zz = out + size * i;
+
+ int n = size;
+ while (n > 0)
+ {
+ size_t vl = __riscv_vsetvl_e32m8 (n);
+ vfloat32m8_t _xx = __riscv_vle32_v_f32m8 (xx, vl);
+ vfloat32m8_t _yy = __riscv_vle32_v_f32m8 (yy, vl);
+ vfloat32m8_t _zz = atan2_ps (_xx, _yy, vl);
+ __riscv_vse32_v_f32m8 (zz, _zz, vl);
+ n -= vl;
+ xx += vl;
+ yy += vl;
+ zz += vl;
+ }
+ }
+}
--
2.25.1
