Since the parameter vl of XTheadVector does not support immediate numbers, we need to put it in the register in advance. That generates the initial code correctly.
PR 116593 gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (function_expander::add_input_operand): Put immediate for vl to GPR for XTheadVector. gcc/testsuite/ChangeLog: * g++.target/riscv/xtheadvector/pr116593-1.C: New test. * g++.target/riscv/xtheadvector/xtheadvector.exp: New test. --- gcc/config/riscv/riscv-vector-builtins.cc | 16 +++++++- .../riscv/xtheadvector/pr116593-1.C | 12 ++++++ .../riscv/xtheadvector/xtheadvector.exp | 37 +++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/riscv/xtheadvector/pr116593-1.C create mode 100644 gcc/testsuite/g++.target/riscv/xtheadvector/xtheadvector.exp diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index d2fe849c693e..b77f0b1567c1 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4120,7 +4120,21 @@ function_expander::add_input_operand (unsigned argno) { tree arg = CALL_EXPR_ARG (exp, argno); rtx x = expand_normal (arg); - add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x); + + /* Since the parameter vl of XTheadVector does not support + immediate numbers, we need to put it in the register + in advance. */ + if (TARGET_XTHEADVECTOR + && CONST_INT_P (x) + && base->apply_vl_p () + && argno == (unsigned) (call_expr_nargs (exp) - 1) + && x != CONST0_RTX (GET_MODE (x))) + { + x = force_reg (word_mode, x); + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x); + } + else + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x); } /* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single patter. diff --git a/gcc/testsuite/g++.target/riscv/xtheadvector/pr116593-1.C b/gcc/testsuite/g++.target/riscv/xtheadvector/pr116593-1.C new file mode 100644 index 000000000000..6590dcbe5030 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/xtheadvector/pr116593-1.C @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */ + +#include <riscv_vector.h> + +vint32m1_t foo (vint32m1_t vs2, vint32m1_t vs1) +{ + return __riscv_vadd_vv_i32m1(vs2, vs1, 3); +} + +/* { dg-final { scan-assembler-times "li\ta\[0-9\],3\n" 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/xtheadvector/xtheadvector.exp b/gcc/testsuite/g++.target/riscv/xtheadvector/xtheadvector.exp new file mode 100644 index 000000000000..40c868b0d805 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/xtheadvector/xtheadvector.exp @@ -0,0 +1,37 @@ +# Copyright (C) 2023-2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Test the front-end for C++. +# We don't need to test back-end code-gen in RV32 system for C++ +# Because it is already tested in C. +# Exit immediately if this isn't a RISC-V target. +if ![istarget riscv*-*-*] then { + return +} + +# Load support procs. +load_lib g++-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] "" "" + +# All done. +dg-finish -- 2.25.1