On Sun, Dec 15, 2024 at 1:31 AM Jeff Law <jeffreya...@gmail.com> wrote: > > > > On 12/9/24 1:56 AM, Kito Cheng wrote: > > This patch set implements the proposal from riscv-c-api-doc[1]. > > It adds two constraints and one modifier with the goal of improving the user > > experience for `.insn`, making it easier for users to experiment with new > > ISA > > extensions. > > > > A quick summary of this patch set: > > > > - Add R constraint for even-odd pairs of general-purpose registers. > > - Add cr and cf constraints for RVC-compatible registers. > > - Add N modifier for the raw encoding of a register. > > > > The c constraint and N modifier were already in use before, but only > > internally. > > Therefore, I believe it is safe to rename them for broader use. > > > > [1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/92 > > > > Kito Cheng (5): > > RISC-V: Rename constraint c0* to k0* > > RISC-V: Add cr and cf constraint > > RISC-V Rename internal operand modifier N to n > > RISC-V: Implment N modifier for printing the register number rather > > than the register name > > RISC-V: Add new constraint R for register even-odd pairs > ps. I think it's pretty unlikely the xtreme-header failures from > pre-commit CI are related to this change. But I'd do a quick check > before committing.
Tried two different servers, but couldn't reproduce either, so I pushed to the trunk :) > > jeff > >
