Apparently I forgot to attach the testcase, will put in v2 or put it
when committing to the trunk.
On Mon, Dec 9, 2024 at 5:06 PM Kito Cheng <kito.ch...@sifive.com> wrote:
>
> Although this constraint is not currently used for any instructions, it is
> very
> useful for custom instructions. Additionally, some new standard extensions
> (not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this
> constraint. Therefore, I believe there is sufficient justification to add it
> now.
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md (R): New constraint.
> * doc/md.texi: Document new constraint `R`.
> ---
> gcc/config/riscv/constraints.md | 4 ++++
> gcc/doc/md.texi | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2dce9832219..ebb71000d12 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -28,6 +28,10 @@ (define_register_constraint "f" "TARGET_HARD_FLOAT ?
> FP_REGS :
> (define_register_constraint "j" "SIBCALL_REGS"
> "@internal")
>
> +(define_register_constraint "R" "GR_REGS"
> + "Even-odd general purpose register pair."
> + "regno % 2 == 0")
> +
> ;; Avoid using register t0 for JALR's argument, because for some
> ;; microarchitectures that is a return-address stack hint.
> (define_register_constraint "l" "JALR_REGS"
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 4ca562266f2..83647b2126d 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -3667,6 +3667,9 @@ RVC general purpose register (x8-x15).
> RVC floating-point registers (f8-f15), if available, reuse GPR as FPR when
> use
> zfinx.
>
> +@item R
> +Even-odd general purpose register pair.
> +
> @end table
>
> @item RX---@file{config/rx/constraints.md}
> --
> 2.34.1
>
